在本篇論文中，將提出一種用以分析加法器(based on NAND2 gate)在不同的位元數下，它的延遲分佈各為多少數量，及分析雙軌骨牌加法器Dual Rail Domino Adder (DRDA)在不同位元數下，Positive 及 Negative path 的延遲分佈各為多少數量的方法論。另外，相較於同步電路的最壞情況設計，非同步電路的平均延遲時間是其最顯著的優點。
因此，我們提出一種”適用於非同步加法器的預先完成偵測電路”稱為“Advanced Completion Detection for Asynchronous Adders (ACDAA)”。此外，為了比較此預先完成偵測電路的效能，進而再設計一個加法器用以比較相同一個完成偵測電路用於不同的非同步加法器其效能的差異。我們所提的ACDAA，利用Carry Look-ahead Adder(CLA)及Manchester Carry Chain的優點，迅速產生進位，且大幅度降低使用CLA時所需的面積。
本篇論文所提出的ACDAA與CLA及雙軌骨牌加法器在4位元共256種8位元共65536種輸入的條件下作了比較，用4位元及8位元架構比較的原因在於可以將所有的電路結構及input pattern都詳細分析並加以說明。結果發現本篇論文所提出的預先完成偵測電路在4-bit的條件下與 CLA相比平均速度快43%、但功耗增加21%、整體的Power Delay Product(PDP)可減少33%。而與DRDA相比速度快18%、功耗增加2.28倍、整體的PDP增加1.87倍。

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