功率消耗已經成為了摩爾定律的主要挑戰，然而單電子電晶體(SET)在室溫底下因為其在運作時的超低功率消耗，已經被提出做為一個有希望延續摩爾定律的裝置。一個針對SET架構的自動化映射(mapping)方法在近期已經提出來使的設計的實現變得容易。在這篇論文中，我們提出了包含變數重序(variable reordering)、積項重序(product term reordering)以及映射限制放寬技巧的一個有效的改良式映射方法用來縮小映射的SET陣列的面積。實驗結果顯示我們的改良式方法在映射後的SET陣列上與之前的最先進的作法相比，針對一組MCNC以及IWLS 2005的測試基準來看在映射時間上獲得了299倍的加速並且在六角型個數上節省了81%。此外，實驗結果也展示了我們的方法與暴力法(brute force approach)針對一些可執行的測試基準相比之下的效率。

Power consumption has become one of the primary challenges
in meeting Moore's law. However, the Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption during operation. An automated mapping approach for the SET architecture has been proposed recently for facilitating design realization. In this paper, we propose an efficient enhanced mapping approach consisting of variable reordering, product term reordering, and mapping constraint relaxation techniques to minimizing the area of mapped SET arrays. The experimental results show that our enhanced approach obtains a speedup of 299 times on the mapping time and saves 81\% hexagon count in the mapped SET array compared to the state-of-the-art approach for a set of MCNC and IWLS 2005 benchmarks. Additionally, the experimental results demonstrate the effectiveness of our approach compared with a brute force approach for some affordable benchmarks.

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