H.264/AVC是目前最新的壓縮標準。它主要著重在視訊的壓縮跟網路上的強健傳輸。H.264與MPEG-2 以及MPEG-4在相同的視訊品質之下，各可以達到省下大約60% 跟40%的碼率。 因為H.264這種高壓縮效率，使得他在很多的應用如高畫質 DVD、數位電視、數位攝影機、視訊電話以及網路視訊傳輸等都被使用。然而因為H.264的高複雜度使得其無法即時完成編碼。所以如何設計一個高效能且能及時運作的框內壓縮器將是框內壓縮的重要課題之一。
在本篇論文中，我們提出了兩種新的框內壓縮器設計。在這兩個設計中，對於亮度九種Intra4x4模式、四種Intra16x16模式以及彩度四種Intra_chroma模式皆有實踐。
第一個針對簡單應用的設計中，我們提出一種新的框內預測器，除了Intra16x16 平面模式之外可以支援大部分預測模式。我們亦提出一個簡單的方式來實踐intra16x16平面模式。這些預測器每個週期可以產生兩個圖素。當這兩個預測器搭配一個緩衝器的時候，所有的預測模式在這個4x4的方塊中都可以透過適當的安排位置而可以使全部的預測模式可以在最多五個週期中。在這個設計中，我們針對來自鄰近4x4方塊的圖素無法即時重建的問題提出重新改變預測模式順序來解決這個問題。很幸運的，因為Intra4x4模式完才接著Intra16x16模式，所以我們能夠利用分離預測部分跟CAVLC部分的緩衝器來儲存較佳模式的16x16殘餘值資料。只要熵編碼的時間夠快我們就可以省下重新重建最佳模式殘餘值的時間。
在針對高性能應用設計中，我們使用第一個設計的架構，但是加入碼率失真最佳化。我們計算模式訊息以及殘餘值編碼的碼率來當作全部的碼率以達到高的壓縮效能。我們提出一個有效又快速的方法來計算這些殘餘值的碼數。因為碼率的預測會造成模式決策路徑變更長，因此我們亦提出一個改變4x4方塊預測順序以及在4x4方塊中預測模式的先後順序來解決這個長等待的時間。
我們使用Xilinx多媒體版來實踐設計的原型而設計的最大可操作頻率為100MHz，大於720x480大小的序列所需的49MHz。

H.264/AVC is the latest video compression standard. It concentrates on video compression and robust transmission support over networks. H.264/AVC could achieve about 60% bit-rate saving over MPEG-2, and about 40% bit-rate saving over MPEG-4 at the same video quality. Because of its high compression efficiency, H.264 attracts high interest for many applications such as High Definition DVD, Digital TV, Digital Camcorders, Camera Phone, Internet video streaming, and others. However, H.264’s complicated encoding process cannot guarantee real-time coding implementation. Therefore, how to design a high efficient intra coder operating in real time is one of the most important things in the H.264 intra encoding issue.
In this thesis, we propose two designs of H.264 intra frame coding circuit. In these two designs, nine Intra4x4, four Intr16x16 prediction modes for luminance samples and four Intra_chroma prediction modes for chrominance samples are implemented.
In the first design for simple applications, we propose a new architecture of intra prediction generator to support most prediction modes except Intra16x16 plane mode and we also propose a simple way to implement Intra16x16 plane mode. The predictor can produce two pixels on average in every cycle. When these two predictors are combined with an arrangement of “fun_unit_buffer” in different modes, all the prediction modes in 4x4MB can be produced in at most five cycles. In this design, we also propose to solve the problem that the neighboring pixels from previous 4x4 MB cannot be reconstructed in time by reordering the prediction mode selections. Fortunately, because the prediction orders in Intra16x16 mode are after the orders in all Intra4x4 modes, we can use two 16x16 MB buffers as MB pipeline between prediction part and CAVLC part to store the 16x16 residual data for better mode and current mode as long as the entropy coding is fast enough. In this way, we can save the clock cycles required by reconstructing the best modes in Intra4x4 or Intra16x16 modes.
In the second design for high performance applications, we use the architecture of the first design in this thesis but add the rate distortion optimization part. We calculate the total bits needed by mode information and residual data to get high compression performance. We propose an efficient and fast way to calculate the bits needed by the residual data, which are the critical part in the design. The rate estimation would cause the mode decision path longer. Therefore, we also propose a way to change the 4x4MB prediction order in the 16x16 MB and reorder the mode selections, so that we can solve the long waiting time problem.
The prototype design is implemented using Xilinx multimedia board and the design limitation is 100MHz in the worst case, which is higher than the required frequency, 49MHz, in 720x480 size frame.

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