參考電路至今已被研究多年，隨著可攜式電子產品發展，其低電壓小電路成為目前的研究中心。而目前參考電路以BJT或MOS為溫度補償元件，經設計以得到低溫度相關電壓輸出；然而電路在考慮功率消耗或運算放大器負載寄生電容及抵補電壓效應下，並聯在它們旁邊的電阻會佔整個晶片面積相當大比例。而參考電路對製程敏感度高，因此在晶片製作中會隨著製程變化使參考電壓產生誤差，其誤差大小會影響後段應用電路運作情形。
本研究主題主要針對上述問題，提出一個新的參考電壓電路並提供一個參考電壓電路受製程不匹配影響的分析方式，我們分別設計一階、二階溫度補償帶差參考電路，其電路採用電流鏡作為溫度補償以減少晶片面積及降低運算放大器的低補電壓；並採用誤差源來分析在雙載子電晶體、電阻與電流鏡不匹配下參考電壓電路變化大小。設計電路已使用台積電標準0.18um CMOS製程實現，一階電路補償電路量測結果，最小工作電壓1.2V，產生的輸出電壓為446mV，量測溫度範圍為25℃~125℃，溫度係數215ppm/°C，晶片面積0.023 mm2；而二階電路量測結果校正後在溫度範圍25~125℃與供應電壓從1~2V變化下，溫度係數變動範圍62ppm/℃，晶片面積0.06 mm2。

Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. The bandgap reference circuits base on BJT and MOS for temperature compensation in recent years. The reference voltage is designed a low sensitivity voltage for temperature and supply voltage. However, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exist. The reference circuit is influenced by process variation. It is induced error voltage by process variation on reference voltage. The magnitude of the error voltage will influence the back-end of circuits on work.
This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A way of prediction on process mismatch will be presented. We design the first order and second order temperature compensation bandgap voltage reference circuits. Their temperature compensation based on current mirror to reduce the chip area and have a low offset voltage on op-amp. We used the error source to analyze the magnitude of reference voltage variation on BJT, resistances and current mirror mismatch. Besides, it has been implemented by a 0.18μm CMOS process. The measurable results of the first order temperature compensation circuits shows that the temperature coefficient is 215 ppm/℃ and produce a output reference voltage 446mV under the temperature range from 25 to 125 ℃ on the minimum supply voltage 1.2V. The chip area is 0.023 mm2. The measurable results of the second order temperature compensation circuit shows that the variation of temperature coefficient is 62 ppm/℃ under the temperature range from 25 to 125 ℃ and a supply voltage variation from 1 to 2V. The chip area is 0.06 mm2.

[1] D. Hilbiber, “A new semiconductor voltage standard,” ISSCC Dig. Of Tech. Papers, pp.32-33, Feb. 1964.
[2] R. Widlar, “New developments in IC voltage regulators,” ISSCC Dig. Of Tech. Papers, pp. 158-159, Feb. 1970.
[3] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-State Circuits, vol. 8, pp. 222-226, June 1973.
[4] D. A. Johns and K. Martin, “Analog integrated circuit design,” 1st ed. New York: Wiley & Sons, 1997.
[5] K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE J. Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.
[6] R. Dehghani and S. M. Atarodi, “A new low voltage precision CMOS current reference with no external components,” IEEE Trans. Circuits Syst.Ⅱ, vol. 50, pp. 928-932, Dec. 2003.
[7] Inyeol Lee, Gyudong Kim and Wonchan Kim, “Exponential Curvature -Compensated BiCMOS Bandgap References,” IEEE J. Solid-State Circuits, vol. 29, pp. 1396-1403, Nov. 1994.
[8] K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE J. Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.
[9] Gabriel A, Rincon-Mora and Phillip E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature Bandgap Reference,” IEEE J. Solid-State Circuits, Vol. 33, 1551-1554, Oct. 1998.
[10] P. Malcovati, F. Maloberti, C. Fiocchi and M. Pruzzi, “Curvature-Compensated BiCMOS Bandgap with 1-V Supply Voltage,” IEEE J. Solid-State Circuits, Vol. 36, pp. 1076-1081, Jul. 2001.
[11] Q. X. Zhang and L. Siek, “A new 4.3 ppm/℃ voltage reference using standard CMOS process with 1V supply voltage,” Proc. IEEE Int. Symp. Circuits and Systems, Vol. 5, pp. 4249-4252, May 23-26, 2005.
[12] M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” IEEE Trans. Circuits Syst. Ⅰ, vol. 48, pp. 876-884, Jul. 2001.
[13] K. N. Leung and P. K. T. Mok, “A CMOS voltage reference based on weighted △VGS for CMOS low-dropout linear regulators,” IEEE J. Solid-State Circuits, vol. 38, pp. 146-150, Jan. 2003.
[14] T. Grotjohn and B. Hoefflinger, “A parametric short-channel MOS transistor model for subthreshold and strong inversion current,” IEEE J. Solid-State Circuits, vol. 19, pp. 100-112, Feb. 1984
[15] M. S. Kim et al., “Optical subthreshold current method for extracting the interface states in MOS systems,” IEEE Trans. Electron Device Letters, vol. 25, no. 2, pp. 101-103, Feb. 2004.
[16] Y. Hu and M. Sawan, “A 900 mV 25 μW high PSRR CMOS voltage reference dedicated to implantable micro-devices,” Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 373-376, May 25-28, 2003.
[17] T. Ytterdal, “CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V,” Electronics Letters, vol. 39, pp. 1427-1428, 2 Oct. 2003.
[18] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design,” 2nd ed. New York: Oxford, 2002.
[19] E. Bruun and P. Shah, “Dynamic range of low-voltage cascode current mirrors,” Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 1328-1331, April 28- May 3, 1995.
[20] E. Sackinger and W. Guggenbuhl, “A high-swing, high-impedance MOS cascode circuit,” IEEE J. Solid-State Circuits, vol. 25, pp. 289-298, Feb. 1990.
[21] Vishal Gupta and Gabriel A. Rincon-Mora, “Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap References,” Proc. 6th Int. Symp. Quality Electronic Design, pp. 503-508, Mar. 21-23, 2005.
[22] Patrick G. Drennan, Colin C. McAndrew and John Bates, “A Comprehensive BJT Mismatch Model,” Proc. Bipolar/BiCMOS Circuits and Technology Meeting, pp. 83-86, 27-29 Sept. 1998.
[23] Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen and Herman E. Maes, “ An Easy-to-Use Mismatch Model for the MOS Transistor,” IEEE J. Solid-State Circuits, Vol. 37, pp. 1056-1064, Aug. 2002.
[24] U. Gatti, F. Maloberti and V. Liberali, “Full stacked layout of analogue cells,” Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 1123-1126, May 1989.
[25] E. Malavasi, D. Pandini and V. Liberali, “Optimum stacked layout for analog CMOS ICs,” in Proc. IEEE Int. Conf. Custom Integrated Circuits, pp. 17.1.1-17.1.4, May 1993.
[26] J. Bruce, H. Li and M. Dallabetta, “An analog layout assistant for matched and balanced CMOS components,” Proc. IEEE Int. ASIC Conference and Exhibit, pp. 267-270, Sept. 1995.
[27] Chris Taillefer and Chunyan Wang, “Current Mirror Compensation for Transistor Mismatch,” Proc. IEEE Int. Symp. Circuits and Systems, pp. 509-512, May 2000.