Investigation of Reliability Issues in a SONOS Flash Memory Cell

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研究生：	廖意瑛 Liao, Yi-Ying
論文名稱：	Investigation of Reliability Issues in a SONOS Flash Memory Cell 矽氧化氮氧化矽快閃記憶元件可靠度問題之研究
指導教授：	洪勝富 Horng, Sheng-Fu
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2009
畢業學年度：	98
語文別：	英文
論文頁數：	116
中文關鍵詞：	Charge pumping 、Flash memory 、low frequency 、SONOS 、variable amplitude 、retention loss 、discrete dopant fluctuation 、FinFET
相關次數：	點閱：3 下載：0
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在本論文中，我們提出一個新型的可變振幅低頻式電荷幫浦 (VALFCP)技術來描述矽氧化氮氧化矽 (SONOS) 快閃記憶元件中氮化矽層缺陷的能量和空間分布。此外，亦使用此VALFCP 技術來研究氧化層和氮化矽層的缺陷經過多次的資料寫入／抹除操作後的特性。我們也利用二維 TCAD模擬器來探討分離摻雜物擾動對於SONOS 元件保存能力的影響。
在第二章中，我們提出了新型的VALFCP 技術，此技術包含一改良後的電荷幫浦量測方法論和一數值模型，可以從電荷幫浦量測資料中萃取出空間和能量的缺陷分布。此數值模型根據Shockley-Read-Hall-like 電荷穿隧捕捉，使電荷幫浦電流和氮化矽缺陷的能量和空間分布產生關聯性。改變電荷幫浦量測方法的頻率和脈衝振幅，可以萃取出以缺陷空間和能量為函數的氮化矽層缺陷密度。在第三章中，我們利用VALFCP 技術來探討在SONOS快閃記憶元件中多次的資料寫入／抹除操作對缺陷產生的影響。我們觀察到在多次的資料寫入／抹除操作後會在氧化層和氮化矽層產生新的缺陷，也會對元件保存能力造成極大的衰退。氧化層和氮化矽層的缺陷密度的增加量遵守指數定律並以資料寫入／抹除次數為函數。我們也觀察到經由寫入以及抹除操作後所產生的氧化層和氮化矽層的缺陷是不穩定的，且高溫儲存的過程中會迅速逸失。
在第四章中，探討分離摻雜物擾動對於45奈米世代以下SONOS為結構之快閃記憶元件的影響。除了已知臨界電壓的擾動之外，寬廣的臨界電壓分布也會影響元件的保存能力，並導致在22奈米世代以下，平面型SONOS快閃記憶元件嚴重的可靠度問題。本篇論文也探討了分離摻雜物擾動對於鰭式場效電晶體 (FinFET) 的影響。具有幾乎無摻雜物通道的FinFET SONOS快閃記憶元件驗證可成為22奈米世代以下 SONOS技術的趨勢。

In this dissertation, we propose a new VALFCP (variable amplitude low-frequency charge pumping) technique to characterize the nitride trap energy and spatial distributions in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory cells. Besides, the VALFCP technique is utilized to investigate effects of P/E cycles on nitride/oxide trap properties. We also study the effects of dopant fluctuation on SONOS cell retention by using 2D TCAD simulations.
In chapter 2, we propose a new VALFCP technique including a modified charge pumping measurement methodology and a generalized numerical model, which allows extracting the spatial and energy trap distributions from the charge pumping data. A numerical model based on Shockley-Read-Hall-like electron tunneling capture is used to correlate a charge pumping current with nitride trap energy and position. By changing frequency and pulse amplitude in charge pumping measurement, a nitride trap density as a function of trap position and energy can be extracted. In chapter 3, influences of program/erase (P/E) cycles on the defect generation in a SONOS flash memory cell are studied by using the VALFCP technique. We observe that P/E cycles would generate new oxide and nitride traps, and degraded cell retention is observed. Besides, the increase of oxide and nitride trap densities follows a power law behavior as a function of P/E cycles. We also observe that these stress-created oxide and nitride traps are unstable and will be eliminated rapidly during high temperature storage.
In chapter 4, the effects of discrete dopant fluctuation in sub-45-nm SONOS flash memory cells are studied. In addition to the well-known fluctuation in threshold voltage, the wide threshold voltage distribution also affects cell retention, which results in a severe reliability problem in planar SONOS flash memory cells beyond the 22 nm generation. Similar discrete dopant effects are observed in the fin field-effect transistor (FinFET) structure. The FinFET SONOS flash memory cell having a nearly un-doped channel is shown to be promising for sub-22-nm SONOS technologies.

Chinese Abstract
English Abstract                                        Acknowledges                                            Contents
Table Captions                                          Figure Captions

Chapter1 Introduction
1-1.Introduction of Floating gate Flash Memory Cell
1-2.Introduction of SONOS Memory Cell
1-3.Current issues of SONOS Memory Cell
1-4.Organization of this Dissertation

Chapter2 Profiling of Nitride Trap Energy Distribution in SONOS Flash Memory by Using a Variable Amplitude Low-Frequency Charge Pumping Technique
2-1.Introduction
2-2.Sample preparation
2-3.Conventional charge pumping technique for interface trap
characterization
2-4.Application of low frequency charge pumping measurement for the characterization of near-interface traps
2-5.VALFCP technique and characterization in SONOS flash memory cells
2-5-1.Definition of the charge profile
2-5-2.The relationships between xm and fcp and SiN and VH
2-5-3.Characterization of trap density by charge pumping current
2-5-4.3D distribution of nitride trap
2-6.Limitation of VALFCP technique
2-7.Comparison of VALFCP technique and retention profiling method
2-8.Conclusion

Chapter3 The Effects of Program/Erase Cycles on the ONO Stack Layer in SONOS Flash Memory Cell Investigated by a Variable Amplitude Low-Frequency Charge Pumping Technique
3-1.Introduction
3-2.The effects of P/E cycles on SONOS cells
3-3.Retention loss model in SONOS cells
3-4.High temperature annealing effects on ONO layers      53
3-5.Conclusion

Chapter4 Investigation of Discrete Dopant Fluctuation Effects in Sub-45-nm Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cell
4-1.Introduction
4-2.Discrete Dopant Fluctuation Effects
4-3.Simulation procedures
4-4.Results and Discussion
4-5.Conclusion

Chapter5 Conclusion
References
Publication List

                                

Chapter 1
[1] K. Kim, “Technology for sub 50-nm node DRAM and NAND Flash Manufacturing,” IEEE IEDM Tech. Dig., pp. 323-326, 2005.
[2] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, pp. 543-545, Nov. 2000.
[3] Y. Shin, J. Choi, C. Kang, C. Lee, K. T. Park, J. S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H. J. Cho, and K. Kim, “A Novel NAND-type MONOS Memory Using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” IEEE IEDM Tech. Dig., pp. 327-330, 2005.
[4] M. H. White, D. A. Adams, J. R. Murray, S. Wrazien, Y. S. Zhao, Y. R. Wang, B. Khan, W. Miller, and R. Mehrotra, “Characterization of Scaled SONOS EEPROM Memory Devices for Space and Military Systems,” Non-Volatile Semi. Memory Workshop, pp. 51-59, 2004.
[5] M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, G. Cohen, “Data Retention Reliability Model of NROM Nonvolatile Memory Products,” IEEE Trans. on Device and Materials Reliability, vol. 4, pp. 404-415, 2004.
[6] W.J. Tsai, N.K. Zous, C.J. Liu, C.C. Liu, C.H. Chen, Tahui Wang, S. Pan, and C.Y. Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” IEEE IEDM Tech. Dig., pp. 719-722, 2001.
[7] W. D. Brown and J. E. Brewer, Eds., Nonvolatile Semiconductor Memory Technology. Piscataway, NJ: IEEE Press, 1998.
[8] Tahui Wang, W.J. Tsai, S.H. Gu, C.T. Chan, C.C. Yeh, N.K. Zous, T.C. Lu, S. Pan, and C.Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-Bit Nitride Storage Flash Memory Cells,” IEEE IEDM Tech. Dig., pp. 169-172, 2003.
[9] S.H Gu, C.W. Hsu, Tahui Wang, W.P. Lu, Y.H.J. Ku, and C.Y. Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells,” IEEE Trans. Electron Devices, vol. 54, pp. 90-97, Jan. 2007.
[10] Y.L. Yang, and Marvin H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures,” Solid-State Electron., vol. 44, pp. 949-958, Sep. 2000.
[11] S.J. Wrazien, Y. Zhao, J.D. Krayer, and Marvin H. White, “Characterization of SONOS Oxynitride Nonvolatile Semiconductor Memory Devices,” Solid-State Electron., vol. 47, pp. 885-891, Sep. 2003.
[12] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electrons Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric,” IEEE Electron Device Letters, vol. 23, pp. 556-558, Sep. 2002.
[13] R.E. Paulsen, R.R. Siergiej, M.L. French, and Marvin H. White, “Observation of Near-Interface Oxide Traps with the Charge-Pumping Technique,” IEEE Electron Device Letters, vol. 13, pp. 627-629, Dec. 1992.
[14] R.E. Paulsen, and Marvin H. White, “Theory and Application of Charge Pumping for the Characterization of Si-SiO2 Interface and Near-Interface Oxide Traps,” IEEE Trans. Electron Devices, vol. 41, pp. 1213-1216, Jul. 1994.
[15] C.E. Weintraub, E. Vogel, J.R. Hauser, N. Yang, V. Misra, J.J. Wortman, J. Ganem, and P. Masson, “Study of Low-Frequency Charge Pumping on Thin Stacked Dielectrics,” IEEE Trans. Electron Devices, vol. 48, pp. 2754-2762, Dec. 2001.
[16] S. Jakschik, A. Avellan, U. Schroeder, and J.W. Bartha, “Influence of Al2O3 Dielectrics on the Trap-Depth Profiles in MOS Devices Investigated by the Charge-Pumping Method,” IEEE Trans. Electron Devices, vol. 51, pp. 2252-2255, Dec. 2004.
[17] C.Y. Lu, K.S. Chang-Liao, P.H. Tsai, and T.K. Wang, “Depth Profiling of Border Traps in MOSFET with High-K Gate Dielectric by Charge-Pumping Technique,” IEEE Electron Device Letters, vol. 27, pp. 859-862, Oct. 2006.
[18] F.L. Yang, J.R. Hwang, H.M. Chen, J.J. Shen, S.M. Yu, Y. Li, and D.D. Tang, “Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS,” Symposium on VLSI Cir. Dig., pp.208-209, 2007.
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[20] V.K. De, X. Tang, and J.D. Meindl, “Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI),” Symposium on VLSI Cir. Dig., pp.198-199, 1996.
[21] A. Asenov, G. Slavcheva, A.R. Brown, J.H. Davies, and S. Saini, “Quantum Mechanical Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations and Lowering in Sub 0.1 micro MOSFETs,” IEEE IEDM Tech. Dig., pp. 535-538, 1999.
[22] T. Mizuno, J.I. Okamura, and A. Toriumi, “Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 2216-2221, Nov. 1994.
[23] T. Hagiwara, K. Yamaguchi, and S. Asai, “Threshold Voltage Deviation in Very Small MOS Transistors Due to Local Impurity Fluctuations,” Symposium on VLSI Cir. Dig., pp.46-47, 1982.
[24] P.A. Stolk, F.P. Widdershoven,, and D.B.M. Klaassen, “Modeling Statistical Dopant Fluctuations in MOS Transistors,” IEEE Trans. Electron Devices, vol. 45, pp. 1960-1971, Sep. 1998.

Chapter 2
[1] J. D. Lee, S. H. Hur, and J. D. Choi, “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, no. 5, pp. 264-266, May. 2002.
[2] Y. S. Shin, “Non-volatile Memory Technologies for Beyond 2010,” Symposium on VLSI Cir. Dig., pp.156-159, 2005.
[3] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, pp. 543-545, Nov. 2000.
[4] Y. Shin, J. Choi, C. Kang, C. Lee, K. T. Park, J. S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H. J. Cho, and K. Kim, “A Novel NAND-type MONOS Memory Using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” IEEE IEDM Tech. Dig., pp. 327-330, 2005.
[5] M. H. White, D. A. Adams, J. R. Murray, S. Wrazien, Y. S. Zhao, Y. R. Wang, B. Khan, W. Miller, and R. Mehrotra, “Characterization of Scaled SONOS EEPROM Memory Devices for Space and Military Systems,” Non-Volatile Semi. Memory Workshop, pp. 51-59, 2004.
[6] W.J. Tsai, N.K. Zous, C.J. Liu, C.C. Liu, C.H. Chen, Tahui Wang, S. Pan, and C.Y. Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” IEEE IEDM Tech. Dig., pp. 719-722, 2001.
[7] Tahui Wang, W.J. Tsai, S.H. Gu, C.T. Chan, C.C. Yeh, N.K. Zous, T.C. Lu, S. Pan, and C.Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-Bit Nitride Storage Flash Memory Cells,” IEEE IEDM Tech. Dig., pp. 169-172, 2003.
[8] S.H Gu, C.W. Hsu, Tahui Wang, W.P. Lu, Y.H.J. Ku, and C.Y. Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells,” IEEE Trans. Electron Devices, vol. 54, pp. 90-97, Jan. 2007.
[9] Y.L. Yang, and Marvin H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures,” Solid-State Electron., vol. 44, pp. 949-958, Sep. 2000.
[10] S.J. Wrazien, Y. Zhao, J.D. Krayer, and Marvin H. White, “Characterization of SONOS Oxynitride Nonvolatile Semiconductor Memory Devices,” Solid-State Electron., vol. 47, pp. 885-891, Sep. 2003.
[11] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electrons Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric,” IEEE Electron Device Letters, vol. 23, pp. 556-558, Sep. 2002.
[12] R.E. Paulsen, R.R. Siergiej, M.L. French, and Marvin H. White, “Observation of Near-Interface Oxide Traps with the Charge-Pumping Technique,” IEEE Electron Device Letters, vol. 13, pp. 627-629, Dec. 1992.
[13] R.E. Paulsen, and Marvin H. White, “Theory and Application of Charge Pumping for the Characterization of Si-SiO2 Interface and Near-Interface Oxide Traps,” IEEE Trans. Electron Devices, vol. 41, pp. 1213-1216, Jul. 1994.
[14] C.E. Weintraub, E. Vogel, J.R. Hauser, N. Yang, V. Misra, J.J. Wortman, J. Ganem, and P. Masson, “Study of Low-Frequency Charge Pumping on Thin Stacked Dielectrics,” IEEE Trans. Electron Devices, vol. 48, pp. 2754-2762, Dec. 2001.
[15] S. Jakschik, A. Avellan, U. Schroeder, and J.W. Bartha, “Influence of Al2O3 Dielectrics on the Trap-Depth Profiles in MOS Devices Investigated by the Charge-Pumping Method,” IEEE Trans. Electron Devices, vol. 51, pp. 2252-2255, Dec. 2004.
[16] C.Y. Lu, K.S. Chang-Liao, P.H. Tsai, and T.K. Wang, “Depth Profiling of Border Traps in MOSFET with High-K Gate Dielectric by Charge-Pumping Technique,” IEEE Electron Device Letters, vol. 27, pp. 859-862, Oct. 2006.
[17] G. Groeseneken , H. E. Maes , N. Beltran and R. F. De Keersmaecker, “A Reliable Approach to Charge-pumping Measurements in MOS Transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 42-53, Jan. 1984.
[18] D. J. Dumin, and J. R. Maddux, “Correlation of Stress-Induced Leakage Current in Thin Oxides with Trap Generation Inside the Oxides,” IEEE Trans. Electron Devices, vol. 40, no. 5, pp. 986-993, May. 1993.
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[20] V. Vasudevan and J. Vasi, “A Simulation of Multiple Trapping Model for Continuous Time Random Walk Transport,” J. Appl. Phys., vol. 74, no. 5, pp. 3224-3230, Sep. 1993.
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[23] Y. Y. Liao, S. F. Horng, Y. W. Chang, T. C. Lu, K. C. Chen, T. Wang, and C. Y. Lu, “Profiling of Nitride-Trap-Energy Distribution in SONOS Flash Memory by Using a Variable-Amplitude Low-Frequency Charge-Pumping Technique,” IEEE Electron Device Letters, vol. 28, no. 9, pp. 828-830, Sep. 2007.
[24] L. D. Landau, and E. M. Lifshitz, Quantum Mechanics, Addison-Wesley, Reading, Mass., pp.174, 1958.
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[26] Y. Wang, and M.H. White, “An Analytical Retention model for SONOS Nonvolatile Memory Devices in the excess electron state,” Solid-State Electron., vol. 49, pp. 97-107, 2005.

Chapter 3
[1] K. Kim, “Technology for sub-50nm DRAM and NAND Flash Manufacturing,” IEEE IEDM Tech. Dig., pp. 323-326, 2005.
[2] K. Kim and G. Jeong, “Memory Technologies for sub-40nm Node,” IEEE IEDM Tech. Dig., pp. 27-30, 2007.
[3] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, pp. 543-545, Nov. 2000.
[4] Y. Shin, J. Choi, C. Kang, C. Lee, K. T. Park, J. S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H. J. Cho, and K. Kim, “A Novel NAND-type MONOS Memory Using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” IEEE IEDM Tech. Dig., pp. 327-330, 2005.
[5] M. H. White, D. A. Adams, J. R. Murray, S. Wrazien, Y. S. Zhao, Y. R. Wang, B. Khan, W. Miller, and R. Mehrotra, “Characterization of Scaled SONOS EEPROM Memory Devices for Space and Military Systems,” Non-Volatile Semi. Memory Workshop, pp. 51-59, 2004.
[6] S. H. Gu, C. W. Hsu, T. Wang, W. P. Lu, Y. H. J. Ku, and C.Y. Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells,” IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 90-97, Jan. 2007.
[7] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C. Y. Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” IEEE IEDM Tech. Dig., pp. 719-722, 2001.
[8] T. Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T. C. Lu, S. Pan, and C. Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-Bit Nitride Storage Flash Memory Cells,” IEEE IEDM Tech. Dig., pp. 169-172, 2003.
[9] J. Bu, and M. H. White, “Effects of Two-Step High Temperature Deuterium Anneals on SONOS Nonvolatile Memory Devices,” IEEE Electron Device Letters, vol. 22, no. 1, pp. 17-19, Jan. 2001.
[10] Y. L. Yang, and M. H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures,” Solid-State Electron., vol. 44, no. 6, pp. 949-958, Jun. 2000.
[11] S. J. Wrazien, Y. Zhao, J. D. Krayer, and M. H. White, “Characterization of SONOS Oxynitride Nonvolatile Semiconductor Memory Devices,” Solid-State Electron., vol. 47, no. 5, pp. 885-891, May. 2003.
[12] Y. Wang, and M. H. White, “An Analytical Retention Model for SONOS Nonvolatile Memory Devices in the Excess Electron State,” Solid-State Electron., vol. 49, pp. 97-107, Jun. 2005.
[13] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electrons Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric,” IEEE Electron Device Letters, vol. 23, no. 9, pp. 556-558, Sep. 2002.
[14] R. E. Paulsen, R. R. Siergiej, M. L. French, and M. H. White, “Observation of Near-Interface Oxide Traps with the Charge-Pumping Technique,” IEEE Electron Device Letters, vol. 13, no. 12, pp. 627-629, Dec. 1992.
[15] R. E. Paulsen, and M. H. White, “Theory and Application of Charge Pumping for the Characterization of Si-SiO2 Interface and Near-Interface Oxide Traps,” IEEE Trans. Electron Devices, vol. 41, no. 7, pp. 1213-1216, Jul. 1994.
[16] A. Chimenton, and P. Olivo, “Reliability of Flash Memory Erasing Operation under High Tunneling Electric Fields,” IEEE Reliability Physics Symp., pp. 216-221, 2004.
[17] J. Bu, and M. H. White, “Retention Reliability Enhacned SONOS NVSM with Scaled Programming Voltage,” IEEE Aerospace Conference Proceedings, pp. 5-2383-5-2390, 2002.

Chapter 4
[1] F.L. Yang, J.R. Hwang, H.M. Chen, J.J. Shen, S.M. Yu, Y. Li, and D.D. Tang, “Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS,” Symposium on VLSI Cir. Dig., pp.208-209, 2007.
[2] H.S. Wong, and Y. Taur, “Three-Dimensional “Atomistic” Simulation of Discrete Random Dopant Distribution Effects in Sub-0.1□m MOSFET’s,” IEEE IEDM Tech. Dig., pp. 705-708, 1993.
[3] V.K. De, X. Tang, and J.D. Meindl, “Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI),” Symposium on VLSI Cir. Dig., pp.198-199, 1996.
[4] A. Asenov, G. Slavcheva, A.R. Brown, J.H. Davies, and S. Saini, “Quantum Mechanical Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations and Lowering in Sub 0.1 micro MOSFETs,” IEEE IEDM Tech. Dig., pp. 535-538, 1999.
[5] T. Mizuno, J.I. Okamura, and A. Toriumi, “Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 2216-2221, Nov. 1994.
[6] T. Hagiwara, K. Yamaguchi, and S. Asai, “Threshold Voltage Deviation in Very Small MOS Transistors Due to Local Impurity Fluctuations,” Symposium on VLSI Cir. Dig., pp.46-47, 1982.
[7] P.A. Stolk, F.P. Widdershoven,, and D.B.M. Klaassen, “Modeling Statistical Dopant Fluctuations in MOS Transistors,” IEEE Trans. Electron Devices, vol. 45, pp. 1960-1971, Sep. 1998.
[8] II H. Cho, II H. Park, J.H. Lee, H. Shin, B.G. Park, and J.D. Lee, “Fin Width Variation Effects on Program Disturbance Characteristics in a NAND Type Bulk Fin SONOS Flash Memory,” Symposium on ISDRS, pp. 1-2, 2007.
[9] Y. Roizin, M. Gutman, R. Yosefi, S. Alfassi, and E. Aloni, “Plasma-Induced Charging in Two Bit per Cell SONOS Memories,” Symposium on Plasma- and Process-Induced Damage, pp. 61-64, 2003.
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