電力電子的發展趨勢是將耐高電壓及高電流的功率元件與低壓的數位或類比電路整合製作成一個單一晶片的功率積體電路。此種功率積體電路增加了電路的可靠度，同時單一晶片的設置更減少了封裝的成本與技術難度，可大量應用在可攜式通訊系統、手提式電腦與馬達驅動電路等要求體積小處理功率大的電子產品中。
本論文將以1.0µm的互補式金氧半電晶體製程(CMOS)為技術基底，設計出耐壓40V以上的互補式功率電晶體，以符合液晶顯示器驅動電路的應用。為了使此製程產生符合要求的功率元件並且維持低壓元件的特性，論文中提出一分離式埋藏層的構想，目的在於改善此次製程中的P型高壓金氧半電晶體之崩潰電壓。由過去的研究顯示，此一元件的耐壓能力由N+埋藏層/P型井/P+汲極之等效貫穿型二極體所決定，高電場區域會落在N+埋藏層與P型井的接面，利用分離式埋藏層結構將有助於降低此接面的高電場現象，大幅提高元件崩潰電壓達40%，而且不造成其它電性參數的退化。

設計過程中將藉由模擬軟體，TSUPREM4以及MEDICI，變動不同的製程與佈局參數，觀察相對應的元件特性變化，以達到與製程相容的最佳化高壓元件設計的目的。最後，我們利用這套製程開發出的高壓元件模型來設計液晶顯示器驅動電路單元，此單元包括位移器電路與輸出級，隨著應用的電壓範圍增高，此電路具有保護閘極氧化層的功能，可避免P型高壓元件的損壞。除了液晶顯示器的應用外，對於許多高功率的數位驅動介面而言，此一電路將是很好的選擇。

[1] H. G. Lin, J. C. Ho, R. R. Iyer, K. Kwong, “Complementary MOS-Bipolar Transistor Structure,” IEEE Trans. Electron Devices, Vol. ED-16, No. 11, Nov. 1969, pp. 945-951.
[2] M. A. Polinsky, O. H. Schade, J. P. Keller, “CMOS-Bipolar Monolithic Integrated Circuit Technology,” 1973 Int. Electron Devices Meeting, pp.229-231.
[3] J. D. Plummer, J. D. Meindl, “A Monolithic 200V CMOS Analog Switch,” J. Solid State Circuits, SC-11, No. 6, Dec. 1976, pp.809-817.
[4] S. Davis, “Simplified Driver, New Applications Spur Plasma-Panel Usage,” Electronic Design News, Sep. 20, 1979, pp. 51-55.
[5] Paul G. Y. Tsui, Percy V. Gilbert, and Shih Wei Sun, “Integration of Power LDMOS into a Low-Voltage 0.5µm BiCMOS Technology,” in IEDM Tech. Dig., 1992, pp.27-30.
[6] Taylor Efland, Satwinder Malhi, Wayne Bailey, Oh Kyong Kwon, Wai Tung Ng, Manolo Torreno, and Steve Keller, “An Optimized RESURF LDMOS Power Device Module Compatible with Advanced Logic Process,” in IEDM Tech. Dig., 1992, pp.237-240.
[7] M. Declercq, F. Clement, M. Schubert, A. Harb, and M. Dutoit, “Design and Optimization of High-Voltage CMOS Devices Compatible with a Standard 5 V CMOS Technology,” IEEE Custom Integrated Circuits Conference, 1993.
[8] Y. Q. Li, C. A. T. Salama, M. Seufert, and M. King, “Submicron BiCMOS Compatible High-Voltage MOS Transistors,” in Proc. 6th Int. Symp. Power Semiconductor Dev. and IC’s, 1994, pp. 355-358.
[9] Y. Q. Li, C. A. T. Salama, M. Seufert, P. Schvan, and M. King, “Integration of High-Voltage NMOS Devices into a Submicron BiCMOS Process Using Simple Structural Changes,” in IEDM Tech. Dig., 1994, pp. 403-406.
[10] Taylor Efland, Peter Mei, Dan Mosher, Bob Todd, “Self-Aligned RESURF to LOCOS region LDMOS Characterization shows Excellent Rsp vs BV Performance,” IEEE, 1996.
[11] Min Liu, C. A. T. Salama, P. Schvan, and M. King, “A Fully Resurfed,BiCMOS- Compatible, High Voltage MOS Transistor,” IEEE, 1996.
[12] Y. Q. Li, C. A. T. Salama, M. Seufert, P. Schvan, and M. King, “Design and Characterization of Submicron BiCMOS Compatible High-Voltage NMOS and PMOS Devices,” IEEE Trans. Electron Devices, vol. 44, pp. 331-338, 1977.
[13] J. A. Appels, and H.M.J. Vaes, “High Voltage Thin Layer Devices (RESURF DEVICES),” IEDM Tech. Dig., pp. 238-239, 1979.
[14] A. Nezar, and C. A. T. Samala, “Optimization of The Breakdown Voltage in LDMOS Transistors Using Internal Field Rings,” IEEE Trans. Electron Device, Vol. ED-38, No. 7 pp. 1676-1680, July 1991.
[15] C. Conterio, P. Galbiati, M. Palmieri, L. Vecchi, “LDMOS Implementation by Large Angle Tilt Implant in 0.6um BCD5 Process, Flash Memory Compatible,” ISPSD Proceedings, pp. 75, 1996.
[16] S. Whiston, D. Bain, A. Deignan, J. Pollard, C. Ni Chleirigh, C. Musgrave M. O’Neill, “Complementary LDMOS Transistors for a CMOS/BiCMOS Process,” ISPSD Proceedings, 2000.
[17] Shuming Xu, Yuanzheng Zhu, Pang-Dow Foo, Yung C. Liang, and Johnny. K. O. Sin, “Folded Gate LDMOS with Low On-Resistance and High Transconductance,” ISPSD Proceedings, 2000.
[18] Z. Parpia, J. Mena, and C. A. T. Salama, and R. A. Hadaway, “A CMOS- Compatible High-Voltage IC Process,” IEEE Trans. Electron Devices, vol.35, pp. 1687-1694, 1988.
[19] S. Colak, “Effect of Drift Region Parameters on The Static Properties of Power LDMOST,” IEEE Trans. Electron Devices, vol. ED-28, pp. 1455-1466, 1981.
[20] V. P. O’Neil and P. G. Alonas, “Relation Between Oxide Thickness and The Breakdown Voltage of a Planar Junction with Field Relief Electrode,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1098-1100, 1979.
[21] Zahir Parpia, and C. Andre T. Samala, “Optimization of RESURF LDMOS Transistor: An Analytical Approach,” IEEE Trans. Electron Device, Vol. ED-37, No. 3, pp. 789-795, March 1990.
[22] S. K. Ghandhi, Semiconductor Power Devices. New York: Wiley, 1977.
[23] B. Jayant Baliga, Power Semiconductor Devices. 1995.
[24] Jaejune Jang; Amborg T.; Zhiping Yu; Dutton R.W., “Circuit model for power LDMOS including quasi-saturation,” Simulation of Semiconductor Processes and Devices, pp. 15-18, 1999.
[25] Hussein Ballan, High Voltage Devices and Circuits in Standard CMOS Technologies. 1999.