隨著積體電路技術的快速發展，多處理器晶片（chip multiprocessors, CMPs）被廣泛使用於平行應用程序及即時應用程序。對於多處理器晶片而言，隨著晶片上處理器數量的持續增加，為了達到高性能及高處理能力（throughput），有效率的溝通是不可或缺的。因此，連接架構的設計對於整體系統的性能、面積及功率消耗發揮了重要的作用。由於晶片網絡（network-on-chip, NoC）和傳統的晶片上匯流排（on-chip bus）架構有其各自的優缺點，我們必需考慮系統的性能要求及應用程序的特性，以設計出適當的網絡連接架構。本論文針對多處理器晶片及多執行緒應用程序（multi-threaded application）提出並評估三種叢集式的連接架構：（1）叢集晶片網路架構，（2）階層匯流排架構，和（3）混合架構。實驗結果顯示對於多處理器晶片及多執行緒應用程序而言，同時考慮到性能及系統的擴充性，在三種叢集式的連接架構之中，叢集晶片網路架構是最實際的選擇。

With the rapid development of silicon technology, chip multiprocessor (CMP) are widely used for parallel applications and real-time applications. For CMPs, as the number of processors on a chip continues to increase, efficient communication is essential for achieving high performance and throughput. Therefore, the design of the interconnection architecture plays an important role in determining the performance, area, and power consumption of the overall system. Because network-on-chip (NoC) and traditional on-chip bus interconnection have their own advantages and disadvantages, we need to consider the system performance requirement and the application properties to design an appropriate network interconnection architecture. In this thesis, for CMPs and multi-threaded applications, we propose and evaluate three cluster-based interconnection architectures: (1) cluster-based NoC architecture, (2) hierarchical bus architecture, and (3) hybrid architecture. The experiment results show that considering both performance and scalability for CMPs and multi-threaded applications, cluster-based NoC architecture is the most practical choice among the three cluster-based interconnection architectures.

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