我們提出一個H.264/AVC的四分之一畫素精準度 (Quarter-pixel Accurate)、可變區塊大小 (Variable Block Size) 移動估計器 (Motion Estimator)。此移動估計器包含全畫素 (Full-pixel) 移動估計以及四分之一畫素移動估計兩大部分，前者是由256個處理單元 (PE) 所構成的二維心脈式陣列 (Systolic Array)，並重複使用先前運算的結果。其採用全域搜尋的方法，並且能在每一個時脈比對一個候選區塊 (Candidate Block)。它算出畫素差值的絕對值總合 (Sum of Absolute Difference) 和移動向量 (Motion Vector)，並傳給四分之一畫素移動估計器。而後者是一個數學模型，負責調整移動向量到四分之一畫素精準度。我們採用台積電0.13μm CMOS的製程來合成設計。在50MHz的頻率以及195K邏輯閘之下，此移動估計器可以處理720x480解析度、每秒30頁的影片。

We propose a variable block-size motion estimator (VBSME) down to quarter-pixel precision for the next generation video coding standard H.264. The proposed motion estimator consists of a full-pixel precision part and a sub-pixel precision part. The former is a 2D systolic array with 256 processing elements (PE) employing a computation result reuse methodology. Its full search algorithm can complete matching a candidate macroblock every clock cycle. It figures out the sum of absolute differences (SAD) and motion vectors (MV) at full-pixel precision for the sub-pixel precision part. The sub-pixel precision part is a mathematical model to refine the SADs and the MVs to quarter-pixel precision. Synthesized into a TSMC 0.13μm CMOS technology, it takes 195K gates at 50MHz to process 720x480 video sequences at 30 frames per second (fps).

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