10Gbps低功率時脈與資料回復電路設計｜國立清華大學博碩士論文庫

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研究生：	曾奕瑋 Tseng, I-Wei
論文名稱：	10Gbps低功率時脈與資料回復電路設計 Low Power Design for the 10Gbps Clock and Data Recovery Circuit
指導教授：	吳仁銘 Wu, Jen-Ming
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	74
中文關鍵詞：	鎖相迴路設計、電壓控制震盪器、頻率與相位回復電路
外文關鍵詞：	PLL, VCO, CDR
相關次數：	點閱：3 下載：0
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近年來，多功能攜帶式系統(如PDA、智慧型手機、筆記型電腦或電子書……等)非常盛行，因此系統單晶片(SoC)設計非常重要。在系統單晶片設計中，功率消耗是一個非常嚴重的問題，此論文提供一個低功率時脈與資料回復電路之設計，用於光纖通訊之系統單晶片中可達低功率消耗之效果。此論文首先介紹一可穩定調整式低功率鎖相迴路設計，設計要點在於將高頻率除頻器與低頻率除頻器做最佳化之調整，更利用增益提升式充電泵浦解決電流不匹配之問題。此外，雙控式電壓控制頻率震盪器，被用來成為調整式鎖相迴路之重要部分。

接著，此論文整合出低功率頻率資料回復電路架構，此架構之所以為低功率消耗之主要特點在於其僅需一栓鎖取樣電路與一邏輯式充店泵浦即可達成相位檢測之目的。使此電路簡單進而達成低功率消耗之目標，成功解決光通系統高速單晶片功率消耗之問題。

此頻率資料回復電路以台積電0.13um之高頻金氧半場效電晶體製程設計，晶片面積僅1.03x0.91mm2。在1.2V之電壓供應下，消耗功率小於30.7mW。相位雜訊於1MHz偏移頻率下，約為-117.43dBc/Hz。

Introduction 1
1 Background and System Construction . . . . . . . . . . 1
2 Design Challenges and Motivations . .  . . . . . . . . 3
3 Thesis Overview . . . . . . . . .. 4
Circuit Background 6
1 Concept of Voltage Control Oscillator . . .  . . . 6
1.1 Barkhausen Criteria . . . . . . . . . . . . 6
1.2 Ring Oscillator . . . . .  . . . . . . . . . . . 7
1.3 LC Oscillator . . . . . .  . . . . . . . . . . . 9
1.4 Voltage Control Oscillator . . . . . . .  . . . . . 11
2 Principle of Phase-Locked Loop . . . . . . . . . . 12
2.1 Architecture of PLL loop . . . . . .  . . . . . . 12
ii
CONTENTS
2.2 Phase and Frequency Detector . . . . . . . 14
2.3 Charge Pump . . . . . . . .. . . . . . 17
2.4 Low Pass Filter . . . . . . .  . . . . . . 19
2.5 Frequency Divider . . . . . . . .. . . . . . . . 21
2.6 CML Latch . . . . . . . . .. . . . . . . . . . . . 22
2.7 TSPC D-Type FlipFlop . . . . . . . . . . . . . . . 23
3 Principle of Clock and Data Recovery Loop . . . . 24
3.1 Phase Detector Circuit . . . .. . . . . . . . . 25
3.2 Concept for Phase Detector Design . . .. . . . . 25
3.3 Hogge Phase Detector . . . . . . . . . . . . 26
3.4 Alexander Phase Detector . . . .. . . . . . 28
3.5 Burst Mode Phase Detector . . . . . . . . . . . . . 28
3.6 Architecture of Clock and Data Recovery . . . . . . 30
3.7 Dual VCO Architecture . . . . . . . . . . . . . . 30
3.8 Dual Loop Architecture . . . . . . . 31
Proposed Low Power Clock Data Recovery Design 32
1 Proposed 18mW 10-GHz Phase-Locked Loop Circuit in 0.13-m CMOS . . . 32
1.1 Introduction .  . . . . . . . . . 32
1.2 Charge Pump with Gain-Boosting . . . . . . . . . . 34
1.3 Components for Frequency Dividers  . . . . 35
1.4 Diversity of VCO with Body Control . . . . 38
iii
CONTENTS
2 Proposed Clock and Data Recovery with Low Power Architecture in 10Gbps 39
2.1 Introduction . . . . .. . . . . . . . . . . . . 39
2.2 Architecture of Clock and Data Recovery Circuit .. 40
2.3 Logical Balance Charge Pump . . . . . . .. . . . . 41
2.4 Charge Pump with Gain-Boosting . . . . . . . . 44
2.5 Dual Control Architecture CDR . . . . .  . . . . . 46
Simulation and Measurement Results 49
1 Simulation Results . . .. . . . . . . . . . . . . . . 49
1.1 Simulation Results of Voltage Control Oscillator .. 49
1.2 Simulation Results of Phase-Locked Loop . . 53
1.3 Simulation of Clock and Data Recovery Loop . . . . 58
2 Measurement Results . . . . . . . . . . . . 63
2.1 Measurement Results of Phase-Locked Loop . . . . . 63
2.2 Measurement Results of Clock and Data Recovery Loop 68
Conclusion and Summary 69
1 Conclusion of Proposed Phase-Locked Loop . . . . . . 69
2 Conclusion of Proposed Clock and Data Recovery Circuit.. 69

                                

[1] International Engineering Consortium http://www.iec.org/
[2] Quarterly Publication in Ministry of Economic Aairs (R.O.C.)
http://www.moea.gov.tw/ ecobook/ms/9106/d63/d634.pdf
[3] IT DataBank Annual Report Services in Market Intelligence and Consulting Institute(MIC)http://mic.iii.org.tw/
[4] International Engineering Consortium http://www.iec.org/
[5] L.E.Larson,"Integrated circuit technology options for RFICs-present status and future directions,"IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 387-399, Mar. 1998.
[6] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.
[7] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill International Edition, 2003.
[8] Harold Chestnut and Robert W. Mayer. Servomechanisms and Regulating System Design.Wiley, New York, 1951.
[9] Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi and Seong Su Park,"A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications,"IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1671-1679, Aug. 2005.
[10] Shuilong Huang and Zhihua Wang," A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm," IEEE International Symposium on Circuits and Systems, pp. 3924-3927, May 2007.
[11] Soh.Lip-Kai, Sulaiman, Mohd-Shahiman, Yuso and Zubaida,"Fast-Lock Dual Charge
Pump Analog DLL using Improved Phase Frequency Detector," IEEE International Symposium on VLSI Design, Automation and Test, pp. 1-5, Apr. 2007.
[12] Y.M.Greshishchev and P.Schvan,"SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application,"IEEE Journal of Solid-State Circuits, vol. 35, no. 9,pp. 1353-1359, Sept. 2000.
[13] Hong-Ih Cong, S.M.Logan, M.J.Loinaz, K.J.O'Brien, E.E.Perry, G.D.Polhemus,J.E.Scoggins, K.P.Snowdon and M.G.Ward,"A 10 Gb/s 16:1 multiplexer and 10 GHz clock synthesizer in 0.25 um SiGe BiCMOS",IEEE International Solid-State Circuits Conference, pp.80-81, Feb. 2001.
[14] S.Y.Choi and D.H.Han,"Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop," IEEE Transactions on Circuits and Systems II, vol. 53, no.10, pp.1022-1025, Oct. 2006.
[15] B. Razavi, "RF Mircoelectronic" PRENTICE HALL PTR Saddle River, J 07458, 1998
[16] P.Heydari and R.Mohanavelu,"Design of ultrahigh-speed low-voltage CMOS CML buffers and latches,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no.10, pp.1081-1093, Oct. 2004.
[17] Yanping Ding and K.O.Kenneth,"A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS,"IEEE Journal of Solid-State Circuits, vol.42, no. 6, pp. 1240-1249, Jun. 2007.
[18] J.Jr, Van Noije and W.A.M.,"A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) Navarro Soares,"IEEE Journal of Solid-State Circuits, vol. 34, no. 1, pp. 97-102, Jan. 1999.
[19] J.Terada, K.Nishimura, S.Kimura, H.Katsurai, N.Yoshimoto and Y.Ohtomo,"A 10.3125Gb/s Burst-Mode CDR Circuit using a DAC,"IEEE International Solid-State Circuits Conference, pp. 226-609, Feb. 2008.
[20] J.Takasoh, T.Yoshimura, H.Kondoh, N.Higashisaka,"A 12.5Gbps half-rate CMOS CDR circuit for 10Gbps network applications," IEEE Symposium on VLSI Circuits, pp. 268-271, June 2004.
[21] H.Nosaka, E.Sano, K.Ishii, M.Ida, K.Kurishima, S.Yamahata, T.Shibata, H.Fukuyama,M.Yoneyama, T.Enoki and M.Muraguchi,"A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector,"IEEE Journal of Solid-State Circuits,vol. 39, no.8, pp. 1361-1365, Aug. 2004.
[22] Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon,Bong-Joon Lee, Deog-Kyoon Jeong,Wonchan Kim, Young-June Park and Gijung Ahn,"A 5-Gb/s 0.25-gm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit,"IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1822-1830, Dec. 2002.
[23] C.R.Hogge,Jr,"A self correcting clock recovery circuit,"IEEE Transactions on Electron Devices, vol. 32, no. 12, pp.2704-2706, Dec. 1985.
[24] Y.S.Choi and D.H.Han,"Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop,"IEEE Transactions on Circuits and Systems II, vol. 53, no. 10, pp. 1022-1025. Oct. 2006.
[25] I-Wei Tseng and Jen-Ming Wu,"An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13um CMOS,"IEEE International Symposium on VLSI Design, Automation and Test,
pp. 227-230, Apr. 2009.
[26] M.Apostolidou, P.G.M.Baltus and C.S.Vaucher,"Phase noise in frequency divider circuits,"IEEE International Symposium on Circuits and Systems , pp.2538-2541, 18-21 May 2008.
[27] S.Gondi and B,Razavi,"Equalization and Clock and Data Recovery Techniques for 10Gb/s CMOS Serial-Link Receivers,"IEEE Journal of Solid-State Circuits, vol 42, no. 9,pp. 1999-2011, Sept. 2007.
[28] Chang-Lin Hsieh, Hong-Lin Chu and Shen-Iuan Liu,"A 10Gb/s inductorless quarter rate clock and data recovery circuit in 0.13um CMOS,"IEEE Asian Solid-State Circuits
Conference, pp. 165-168, Nov. 2009.
[29] I-Wei Tseng and Jen-Ming Wu,"A 10GBps Clock and Data Recovery with Low Power Consumption Architecture,"IEEE Transactions on Circuits and Systems II, In preparation.

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