記憶體內計算（computing in memory；CIM）有效降低傳統處理器計算單
元與記憶體間之資料量，同時也利用記憶體中字元線（word line）與位元
線（bit line）的結構進行巨量的計算，已成為下世代高效能、低功耗人工智
慧計算主要候選人之一。然而其混和訊號（mixed signal）之特性易受設計
變異（variations）影響造成計算結果與預期有相當的誤差。本研究提出以位
元線內積期望值作為晶片誤差校準之基礎，同時透過權重調整降低上述計
算誤差對於神經網路計算推理之正確性影響。我們以關鍵字喚醒（keyword
spotting；KWS）之二元卷積網路之實驗結果可將準確度因變異掉至53.17％
～11.96％之CIM皆提升至70％以上，以文獻中抗變異電路設計與重新訓練等方
法相較，本研究提出之方法在成本、時間上更具有優勢，適合量產CIM採用。

Computing in memory (CIM) effectively reduces the data transformation between the traditional computing unit and memory. It uses the word line and bit line in memory to perform massive calculations. CIM has become one of the candidates for the next generation of high-performance, low-power AI computing. However, CIM's mixed-signal characteristics are vulnerable to variations, resulting in considerable errors in the calculation results. This thesis proposes to use the expected inner product value of the bit line as the basis for the calibration of the chip, and at the same time, reduce the influence of the variations on the correctness of the neural network calculation through weight adjustment. The experimental results of our binary CIM using keyword spotting (KWS) show that under different variation scales, our method significantly improves the accuracies ranging from 11.96\% to 53.17\% to more than 70\%. Compared with methods such as variation-resilient circuit design and retraining in other papers, the proposed method in this thesis has more advantages in cost and time and is suitable for mass production CIM.

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