近年來隨著科技的進步，大眾對於高速資料傳輸逐漸重視且需要
，光纖通訊提供高頻寬介面性質而沒有電訊號傳輸介面的許多缺點，所以光纖通訊系統在資料傳輸上扮演著重要的角色。
本論文分為兩部分，第一部分為利用TSMC 0.18μm CMOS製程來實現3.125Gb/s光接收前端電路。在所設計的電路中，使用差動主動米勒電容(Differential Active Miller Capacitor，DAMC)電路來取代外接式電容可更有效率的使用晶片面積，而此全整合性之設計也可避免掉晶片外部的雜訊干擾，由量測結果可得到，在使用231-1的虛擬隨機位元序列(Pseudo-Random Binary Sequence，PRBS)以及誤碼率(Bit Error Rate，BER)為10-12的測試條件之下，可得到相當精確的交錯點以及最小化的直流偏移量。整體的轉阻增益、功率耗損及晶片面積分別為108.02dBΩ、43.2mW和0.53mm × 0.61mm，量測結果呈現出來的電路效能皆優於其它文獻。
第二部分為光偵測器(Photo Detector，PD)的設計，以TSMC 0.18μm SiGe BiCMOS製程實現高響應度(Responsivity)之光偵測器。利用SiGe異質接面材料特性及光電晶體放大特性，增加光偵測器響應度，量測結果在750nm光源下高達75A/W。

Along with the improvement of technology, people realized the importance and indispensability of high data rate in communications. The Optical Fiber Communication provides the good properties of high bandwidth interface without the problems seen in electrical interface, and therefore the Optical Fiber Communication System plays an important role in modern data transmission.
This thesis can be divided into two parts. One is the design of the analog front-end in a 3.125 Gb/s optical receiver, fabricated in TSMC 0.18μm CMOS technology. The designed optical receiver front-end circuit utilizes high performance differential active Miller capacitor (DAMC) circuits to replace the off-chip capacitors so as to achieve an area-efficient design. The fully integrated design can also avoid off-chip noise interference. The measured results show that it the circuit achieves high precise crossing points and minimal dc offset, at a bit error rate (BER) of 10-12 using the 231-1 pseudo-random bit sequence pattern. The achieved transimpedance gain, power consumption and chip area are 108.02dBΩ, 43.2mW and 0.53mm × 0.61mm, respectively. The results show superior performance when compared with the figures in other works.
The other part of the thesis is the design of high responsivity photodetector, implemented through TSMC 0.18μm SiGe BiCMOS process. The responsivity of photodetector is improved by the properties of SiGe heterojunction and phototransistor and which achieves a measured high value of 75 A/W under a 750nm wavelength light.

[1] 鄒志偉, 光纖通訊, 五南圖書出版股份有限公司, 2011.
[2] 劉秉澄, “應用於10Gb/s之高效能矽鍺限幅放大器設計”, 國立清華大學, 電子工程研究所, 碩士論文, 中華民國九十六年七月.
[3] S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1158–1169, May 2011.
[4] E. Sackinger, Broadband Circuits for Optical Fiber Communication. John Wiley & Sons, Inc., 2005.
[5] B. Razavi, Design of Integrated Circuits for Optical Communication Systems. McGraw-Hill, 2003.
[6] S. M. Park and H.-J. Yoo, “1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit Ethernet applications,” IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp. 112–121, Jan. 2004.
[7] S. Galal et al., “10Gb/s limiting amplifier and laser/modulator driver in 0.18µm CMOS technology,” IEEE J. of Solid-State Circuits, vol. 38, pp. 2138-2146, Dec. 2003.
[8] T. S. Kao, F. A. Musa, and A. Chan Carusone, “A 5-Gbps CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2844–2857, Nov. 2010.
[9] Chia-Ming Tsai, “A 40mW 3 Gb/s self-compensated differential transimpedance amplifier with enlarged input capacitance tolerance in 0.18µm CMOS technology,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 10, Oct. 2009.
[10] Li Zhiqun, Xue Zhaofeng, Chen Lili, Wang Zhigong, and Feng Jun, “40 Gbps, 0.18 μm CMOS front-end amplifier for VSR parallel optical receiver,” IEEE Symposium on Photonics and Optoelectronics. Wuhan, pp. 14-16, Aug. 2009.
[11] F. Aznar, S. Celma, B. Calvo and I. Lope, “A 0.18 µm CMOS integrated transimpedance amplifier-equalizer for 2.5 Gb/s,” IEEE International Midwest Symposium on Circuits and Systems. Seattle, pp. 604-607, Aug. 2010.
[12] Hossein Miri Lavasani, Wanling Pan, Brandon Harrington, Reza Abdolvand, and Farrokh Ayazi, et al., “A 76 dBΩ 1.7 GHz 0.18 μm CMOS tunable TIA using broadband current pre-amplifier for high frequency lateral MEMS oscillators,” IEEE Journal of Solid-State Circuits, Vol. 46, pp. 224-235, 2011.
[13] Filip Tavernier and Michiel Steyaert, “A 5.5 Gbps optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode,” IEEE ESSCIRC, Seville, pp. 542-545, Sept. 2010.
[14] Filip Tavernier and Michel S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 10, Oct. 2009.
[15] 黃吉成, “應用於0.35 µm SiGe BiCMOS 高速光電積體電路之設計技巧”, 國立清華大學, 電子工程研究所, 博士論文, 中華民國九十八年七月.
[16] Huei-Yan Huang, Jun-Chau Chien, and Liang-Hung Lu, “A 10-Gbps inductorless CMOS limiting amplifier with third-order interleaving active feedback,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 5, May 2007.
[17] Wei-Zen Chen, Shih-Hao Huang, Guo-Wei Wu, Chuan-Chang Liu, and Yang-Tung Huang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” IEEE Asian Solid-State Circuits Conference, pp. 396-399, Nov. 2007.
[18] W.-Z. Chen and S.-H. Huang, “A 2.5 Gbps CMOS fully integrated optical receiver with lateral PIN detector,” in Proc. Custom Integrated Circuits Conf., pp. 293–296, Sept. 2007.
[19] 林威成, “標準SiGe BiCMOS製程中光偵測器結構之研究”, 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百年六月.
[20] S. M. Sze, Semiconductor Device Physics and Technology. John Wiley & Sons Inc., 2nd & 3rd.