隨著先進製程技術的衍進，低功率的晶片設計已成為必要的考量。在一個現代SoC設計平台上，記憶體所佔據的面積比例已隨著儲存容量的加大而增加; 因此記憶體所引起的功率消耗，也相對於整體晶片總功率消耗而增加其百分比，約佔整顆晶片40%以上的功率消耗。因此，一個具有高準確度的記憶體功率消耗模型，扮演著一個重要的角色。
藉由我們之前已經提出的”使用多工器導向線性迴歸法對記憶體產生器建構具有外差能力之功率模型”(Extrapolation-Based Power Modeling for Memory Compiler Using MUX-Oriented Linear Regression)，我們把它應用在雙埠靜態隨機存取記憶體(Dual-Port SRAM)的操作模式分類上。在本論文中將會討論實際在雙埠靜態隨機存取記憶體會可能會出現的基線操作組合(Baseline Operation Modes)，並成功的運用對稱性(Symmetry Property)和加法性(Summation Property)使得原本的9種操作模式縮減為3種操作模式，可將模擬時間由原本的1天14分縮短至0.5天。除此之外，一種特殊的操作模式，稱為: 不選取模式(Deselected Mode)，在本論文裡也會被討論，並結合之前的操作模式，使其變成一個更完整操作模式分類來應付實際操作上可能會遇見的各種不同操作模式。另一個重要的考量就是漏電流的功率消耗(Leakage Power Dissipation)，也可以成功的用上述的多工器導向功率模型來建立漏電流的功率消耗模型。
實驗數據顯示，我們提出的所有操作模式的平均功率消耗誤差都在3~6個百分比內，尤其是漏電流的功率消耗只有1.1個百分比的誤差。

In this thesis, we propose the baseline operation modes, which specify these situations of memory power consumption, and used for dual-power SRAM, in reality. This methodology of classification is based on the power mode we proposed previous, MUX-Oriented power modeling, with high accuracy and parameterizeable features. We also apply the symmetry property and summation property to baseline operation modes and succeed in simplifying these modes from nine types to three types only. Besides, a special operation mode, deselected mode, is discussed, and combined with our operation modes to make it stronger and fit for any operations. Leakage power dissipation is an import issue and also be discussed use a white-box methodology in this thesis. Validation set are used to demonstrate that all of these operation modes we proposed have an average predicting error with 3%~6%, and only 1.1% for leakage memory power consumption.

[1]“Artisan Standard Library SRAM Generator User Manual,” Artisan Components, 2004.

[2] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for architectural-level power analysis and optimizations,” Proc. of Int’l Symp. on Comput. Architecture, pp. 83-94, June 2000.

[3] F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, “Global communication and memory optimizing transformations for low power signal processing system,” Proc. of Int’l Workshop on Low-Power Design, pp. 51-56, 1994.

[4] M. Chinosi, R. Zafalon, and C. Guardiani, “Automatic characterization and modeling of power consumption in static RAMs,” Low Power Electronics and Design, August 1998.

[5] S. L. Courmeri and D. E. Thomas, Jr., “Memory modeling for system synthesis,” IEEE Trans. VLSI Systems, vol. 8, pp. 327-334, June 2000.

[6] D. Elleouet, N. Julien, D. Houzet, J.-G. Cousin, and E. Martin, “Power consumption characterization and modeling of embedded memories in XILINX VIRTEX 400E FPGA,” Proc. of EUROMICRO System on Digital System Design, pp. 394-410, 2004.

[7] R. J. Evans and P. D. Franzon, “Energy consumption modeling and optimization for SRAM’s,” IEEE J. Solid-State Circuits, vol. 30, no.5, pp. 571-579, May 1995.

[8] T. Ishihara and K. Asada, “A system level memory power optimization technique using multiple supply and threshold voltages,” Proc. of Asia and South Pacific Design Automation Conf., pp.456-461, 2001.

[9] K. Itoh, K. Sasaki, and Y. Nakagome, “Trends in low-power RAM circuit technologies,” Proc. of IEEE, vol. 83, no. 4, pp. 524-543, April 1995.

[10] M. B. Kamble and K. Ghose, “Analytical energy dissipation models for low power caches,” Proc. of Int’l Symp. Low-Power Design, pp. 143-148, 1997.

[11] U. Ko and P. T. Balsara, “Characterization and design of a low-power, high-performance cache architecture,” Proc. of Int’l Symp. on VLSI Technology, Systems and Applications, pp. 235-238, 1995.

[12] P. E. Landman and J. M. Rabaey, “Architectural power analysis: the dual bit type method,” IEEE Trans. on VLSI Systems, vol. 3, no. 2, pp. 173-187, June 1995.

[13] S. J. Leon, Linear Algebra with Application. Upper Saddle River, NJ: Prentice Hall, 2002.

[14] M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, “IDAP: A tool for high-level power estimation of custom array structures,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 9, pp. 1361-1369, Sept. 2004.

[15] J. Montanaro et al., “A 160-MHz, 32b, 0.5-W CMOS RISC microprocessor,” IEEE J. Solid-State Circuits, pp. 1703-1712, Nov. 1996.

[16] E. Schmidt, G. von Colln, L. Kruse, F. Theeuwen, and W. Nebel, “Memory power models for multilevel power estimation and optimization,” IEEE Trans. on VLSI Systems, vol. 10, no. 2, pp. 106-109, April 2002.

[17] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1985.

[18] W. T. Hsieh, C. C. Yu, and C. N. Liu, “An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model,“ IEICE Trans. on Fundamental of Electronics, Communications, and Computer Science, Vol. E90-A, No. 5, pp. 1038-1044, May 2007.

[19] X. Liang, K. Turgay, and D. Brooks, “Architectural Power Models for SRAM and CAM Structures Based on Hybrid Analytical/Empirical Techniques,” IEEE/ACM International Conference on ICCAD, pp. 824-830, Nov. 2007.

[20] M. Q. Do, L. Edefors, and M. Drazdziulis, “High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process,” 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp. 249-256, Aug. 2007.

[21] M. Q. Do, M. Drazdziulis, P. Larsson-Edefors, and L. Bengtson, “Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays,” 8th International Symposium on Quality Electronic Design, pp. 185-191, March 2007.

[22] A. Gupte, M. Sharma, G.. Varshney, L. Holla, P. Rana, and H. Udayakumar, “Memroy Power Modeling – A Novel Approach,” IEEE Computer Society Annual Symposium on VLSI, pp. 263-268, April 2008.

[23] M. C. Li, C. C. Weng, T. Y. Tai, and S. Y. Huang, “Extrapolation-Based Power Modeling for Memory Compilers Using MUX-Oriented Linear Regression,” VLSI/CAD Symposium, paper #29, August 2008.

[24] S. Borkar. “Design Challenges fro Technology Scaling,” IEE Micro, pp. 23-29, August 1999.