積體電路的佈局方法已經被研究多年，如何在佈局階段增進效能一直以來都是熱門的研究。在此論文當中，對佈局後的積體電路，我們提出一個利用繞線階段資訊，適當的交換正反器位置達到時序增益的演算法。這個演算法包含三個階段，第一階段設計兩個正反器交換時序變化的公式，第二階段根據此公式產生整個電路的正反器交換列表，第三階段則是提出兩種挑選方式去選擇列表中的正反器做交換。另外，我們的演算法結合了net-based和path-based 的架構，可以便利的在時序精準度與執行時間之間做取捨。實驗結果顯示，一個已經被效能導向佈局後的積體電路，我們提出的演算法能在移動距離限制的條件下達到時序增益。

Timing-driven placement is a well-known technique that relocates cells along critical paths to improve timing. Traditional approaches fix timing violation while treating clock skew as given. We propose a flip-flop swapping algorithm for adding useful skew. We derive a gain function reflecting timing slack variation from flip-flop swapping. By employing a hybrid of net-based and path-based structure, it facilitates trade off between timing accuracy and time complexity. We test our approach with the benchmark contents of top three winners of ICCAD 2014 contest.
Experiment results show our placer achieves better timing improvement than their solutions.

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