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研究生： 楊子賢
Tz-Shyan Yang
論文名稱： H.264/AVC Baseline Profile解碼器設計與實現
Design and Implementation of an H.264/AVC Baseline Profile Decoder
指導教授： 陳永昌
Yung-Chang Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 產業研發碩士積體電路設計專班
Industrial Technology R&D Master Program on IC Design
論文出版年： 2007
畢業學年度： 95
語文別： 中文
論文頁數： 65
中文關鍵詞： H.264/AVC 、Baseline Profile 、解碼器
外文關鍵詞： H.264/AVC, Baseline Profile, Decoder
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    • 數位視訊的應用範圍日益廣泛，從視訊會議到高畫質DVD和數位電視都能見到他的蹤影，而H.264/AVC擁有多項獨特的優點，使他優於其他現有的視訊壓縮標準。
    H.264/AVC擁有下列優點：（1）最多可節省50%的位元率：與之前的視訊標準如H.263或是MPEG-4相較下，H.264/AVC最多可節省50%的位元率；（2）高品質視訊：無論位元率的高低，H.264皆可提供一定的良好視訊品質。（3）容錯性（error resilience）：H.264/AVC提供多種工具，可以處理網路的封包遺失。（4）網路友善性：透過網路適應層（Network Adaptation Layer），H.264/AVC位元串很容易就能在不同網路上傳輸。
    但是相對的H.264/AVC卻比現存任何一種視訊壓縮標準都來的複雜，相對的需被解碼資料量也大增，所以設計一個高效能，且能即時運作的解碼器將是一個非常重要的議題。
    在本篇論文中，我們強調的是資料的重複利用（Data reuse）和減少運算時間，來做為設計的主軸，在熵解碼器中，我們設計了兩個機制來減少處理資料的所需時間與合成後的面積。在反轉換單元中，我們利用了矩陣的一些運算特性，使得原本二維的運算，現在只需要利用一維運算即可，增加了設計的方便性。在框間估測單元中，我們採用了一個平行計算內插值的處理架構，再搭配Data reuse memory，使的整體的運算時間更為減少。在框內估測單元中，我們提出了一個除了Intra16x16 plane mode之外皆可支援的預測架構，每個執行週期可以產生四個像素值，再搭配適當輸入的像素位置，可以使所有的預測模式在最多三個執行週期內完成。在去區塊濾波器單元中，我們利用了三塊內部記憶體來儲存將被重複利用的資料，並且加入兩個旋轉暫存器來配合運算，而設計出三階層管線化的架構，更減少了運算時間。
    融合上述的機制後，我們設計出一個三階層管線化的解碼器架構，並且使用UMC 0.18 um製程的技術做合成。合成後邏輯閘數量約為248K，內部記憶體大小約12K，在1.8V的電源下，所耗功率約為156.17mW，可輕鬆支援1920x1080、 4:2:0 、 30fps的影像規格。

    Digital video covers a wide range of video applications such as High Definition DVD , Camera Phone , Digital TV and others. And H.264/AVC has multiple advantages such that it can provide a better compression performance than previous standards.
    The advantages for H.264/AVC are the following :
    (1) Bit-rate saving : Comparing with H.263 and MPEG-4 , it can achieve about 50% bit-rate reduction.
    (2) High quality : H.264/AVC can offer a certain good video quality even in a low bit-rate channel.
    (3)Error resilience : H.264/AVC provides several error resilience tools to deal with the problem of packet-loss.
    (4) NAL : To use the Network Adaptation Layer , H.264/AVC bitstream can
    transmit on different network easily.
    However , H.264/AVC video coding is considerably more complicated than
    precious standards , and also needs much more decoding information. Therefore, how to design a highly efficient real-time decoder and to reduce power consumption are most important things in the field of H.264/AVC code design.
    In this thesis, data reuse and operation time reduction are emphasized in the design. As for the CAVLC Decoder unit , we propose two methods to reduce process cycles and level table storage; for the Inverse Transform unit , we use several matrix identities to reduce process cycles; as to the Intra Prediction unit , we propose a new architecture of intra prediction generator to support most prediction modes except Intra16x16 plane mode , and then we also propose a simple way to implement Intra16x16 plane modee. The Inter-Prediction unit highly exploits the data reuse technique between interpolations of neighboring blocks to save process cycles. Finally,for the Deblocking-Filter unit , we propose a three stage pipeline architecture using three internal memory to store the reusing data to reduce process cycles.
    A prototype design is implemented by Artisan 0.18um standard CMOS cell library with UMC 0.18um technology. The total gate count is about 248K synthesized at 120MHz. The maximum processing capability is an 1920x1080 4:2:0 30Hz video. Totally , about 12K on chip memory are required. The average power consumption is 156.17mW when operating at 120MHz under 1.8V power supply.

    Abstract..............................................................................................................I Table of Contents............................................................................................III List of Figures...................................................................................................V List of Tables................................................................................................VIII 第一章 緒論..................................................1 1.1 視訊標準的演化......................................................1 1.2 研究動機................................................2 1.3 論文架構...............................................2 第二章 H.264/AVC 簡介...............................................4 2.1 H.264壓縮標準簡介.......................................................4 2.1.1 Four profiles....................................................................4 2.1.2 Slices.......................................................................5 2.2 H.264/AVC解碼器簡介........................................................................6 2.3 反轉換（Inverse Transform）................................................................7 2.3.1 反量化（Inverse Quantization）.............................................7 2.4 框內預測（Intra Prediction）...............................................................9 2.4.1 Intra 4x4 mode prediction process for luma samples................9 2.4.2 Intra 16x16 mode prediction process for luma samples..........11 2.4.3 Intra prediction process for chrominance samples..................12 2.5 框間預測（Inter Prediction）.............................................................13 2.5.1 彈性區塊大小（Variable Block Sizes）..............................13 2.5.2 精準度為四分之一像素的移動向量（Quarter Pixel Precision Motion vector）.......................................................15 2.5.3 移動向量估測（Motion Vector Prediction）.......................17 2.6 消除區塊濾波器（Deblocking Filter）..............................................18 2.7 熵編碼（Entropy Coding）..................................................................22 2.7.1 情境適應性可變長度碼（CAVLC）..................................22 2.7.2 指數-葛拉姆（Exp-Golomb）...............................................24 第三章 H.264/AVC解碼器架構設計....................................................28 3.1 H.264/AVC Baseline profile decoder...................................................28 3.2 Entropy decoder stage..........................................................................29 3.2.1 CAVLC decoder.......................................................................30 3.2.2 Inverse Transform....................................................................33 3.3 Inter stage.............................................................................................39 3.3.1 內插（Interpolation）.............................................................40 3.4 Intra stage.............................................................................................46 3.5 Deblocking Filter stage........................................................................53 第四章 實現結果與比較........................................................................57 4.1 系統規格.............................................................................................57 4.2 設計流程.............................................................................................57 4.3 實現結果.............................................................................................59 第五章 結論與未來展望........................................................................62 5.1 結論.....................................................................................................62 5.2 未來展望.............................................................................................62 參考文獻........................................................................................................64 List of Figures 圖 2.1.1-1 H.264/AVC Profiles分類...............................................................................4 圖 2.2-1 H.264/AVC Baseline decoder............................................................................6 圖 2.4.1-1 Intra4x4 modes and their directions...............................................................9 圖 2.4.1-2 Labeling of prediction references.................................................................10 圖 2.4.1-3 Intra4x4mode prediction modes...................................................................10 圖 2.4.2-1 Intra16x16 modes and their reference pixels................................................11 圖 2.5.1-1 Macroblock partition.....................................................................................14 圖 2.5.1-2 Macroblock sub-partition..............................................................................14 圖 2.5.1-3 Partitioning of macroblock...........................................................................14 圖 2.5.2-1 6-tap FIR for Half-pixel position..................................................................15 圖 2.5.2-2 Biliner filter for quarter-pixel position.........................................................16 圖 2.5.2-3 Interpolation scheme for chroma compent...................................................16 圖 2.5.3-1 Current and neighboring partitions...............................................................17 圖 2.6-1 Edge filtering order in a macroblock...............................................................18 圖 2.6-2 Flowchart for determining the boundary strength...........................................19 圖 2.6-3 Luma and chroma boundary strengths.............................................................19 圖 2.6-4 Samples adjacent to vertical and horizontal boundaries..................................20 圖 2.6-5 Subjective views without/with deblocking for the frame................................21 圖 2.7.1-1 Zig-Zag scan order........................................................................................22 圖 2.7.1-2 A CAVLC example......................................................................................23 圖 2.7.2-1 Exp-Golomb Code........................................................................................24 圖 2.7.2-2 The flowchart of reading one macroblock....................................................26 圖 2.7.2-3 The flowchart of reading all coeff. for one macroblock...............................27 圖 3.1-1 Three stage pipeline for H.264/AVC decoder.................................................29 圖 3.1-2 Macroblock-based pipeline scheme.................................................................29 圖 3.2.1-1 The flowchart for CAVLC decoder..............................................................30 圖 3.2.2-1 Butterfly diagram of 1-D 4x4 IDCT.............................................................35 圖 3.2.2-2 Butterfly diagram of 2-D 4x4 IDCT.............................................................38 圖 3.3-1 Hardware architecture of proposed motion compensation..............................39 圖 3.3.1-1 Original interpolation process.......................................................................40 圖 3.3.1-2 A basic separated 1-D interpolation.............................................................41 圖 3.3.1-3 Parallel interpolation process........................................................................42 圖 3.3.1-4 parallel interpolation architecture.................................................................42 圖 3.3.1-5 decoding order..............................................................................................43 圖 3.3.1-6 Fast interpolation architecture......................................................................44 圖 3.3.1-7 Data reuse buffer manager............................................................................44 圖 3.3.1-8 Fast interpolation result................................................................................45 圖 3.4-1 Intra prediction architecture.............................................................................46 圖 3.4-2 Intra general predictor architecture..................................................................47 圖 3.4-3 Intra4x4 DC prediction mode..........................................................................47 圖 3.4-4 Intra4x4 Diagonal down-right prediction mode..............................................48 圖 3.4-5 Timing schedule of position in prediction buffer............................................49 圖 3.4-6 Intra 16x16 prediction buffer...........................................................................50 圖 3.4-7 plane initial positions value.............................................................................51 圖 3.4-8 Timing schedule of Intra16x16 plane prediction mode...................................52 圖 3.5-1 Architecture design for the deblocking filter...................................................53 圖 3.5-2 Local memory organization.............................................................................54 圖 3.5-3 Processing order of boundaries........................................................................55 圖 3.5-4 Timing flow of deblocking filter.....................................................................56 圖 4.2-1 Cell-based VLSI design flow...........................................................................58 圖 4.3-1 Gate-count of the proposed H.264/AVC baseline decoder.............................59 圖 4.3-2 An example of the pipelining schedule...........................................................61 圖 4.3-3 The Throughput analysis.................................................................................61 List of Tables 表 2-1 Scaling factor V....................................................................................................8 表 3.2.1-1 VLC0 table....................................................................................................32 表 3.2.1-2 VLC1 table....................................................................................................33 表 4.1-1 Specification for the proposed design..............................................................57 表 4.3-1 Comparison with other architectures...............................................................60

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