碳化矽因擁有高崩潰電場、高熱導係數與低導通電阻等特性，逐漸被應用於功率金氧半電晶體的研究上。
本論文研究中，我們製作出一個具有場平面保護、RESURF結構結合雙漂移區設計的4H-碳化矽金氧半電晶體於半絕緣基板上。雙漂移區結構設計是將靠近閘極端的漂移區摻雜濃度降低，降低閘極氧化層電場避免氧化層提早崩潰，靠近汲極端保持高摻雜濃度，如此便可使元件擁有較大的崩潰電壓而不犧牲導通電阻。半絕緣基板可避免傳統P型基板產生的基板輔助空乏效應。
與之前研究不同之處為離子佈植活化製程利用石墨披覆層保護避免高溫讓表面平整度變差。閘極氧化層長氧過後使用一氧化氮退火減少氧化層與碳化矽介面間缺陷避免庫倫散射導致遷移率變差。
實驗量測結果顯示，通道長度5μm漂移區80μm的元件崩潰電壓可達3500V，特徵導通電阻值為435 mΩ-cm2。閘極分為圓形與線型兩種設計，線型元件有較大的漏電流與缺陷陷捕效應，推測應為乾蝕刻造成隔離區邊緣上的缺陷所致。

Power MOSFETs in Silicon Carbide (SiC) have the potential of high breakdown, high temperature operation and low specific on-resistance due to its high avalanche breakdown field and large thermal conductivity.
In this thesis, we demonstrate a high-voltage lateral 4H-SiC MOSFET on a semi-insulating substrate with two-zone and field plate structures. Two RESURF zones with lower dose in zone1 close to the gate and higher dose in zone2 close to the drain can reduce the electric field near the gate oxide without increasing the specific on-resistance. Field plates are also employed at the gate and the drain to enhance the breakdown voltage. Semi-insulating substrates are used to avoid substrate assisted depletion effect and the vertical breakdown.
Different from our previous work, we successfully suppress the surface roughening by using a graphite cap during high-temperature activation. In addition, gate oxide annealed in NO ambient is used to passivate the interfaces at SiO2/4H-SiC after thermal oxidation.
From measurements, the best blocking voltage of 3500V with a specific on-resistance of 435 mΩ-cm2 is obtained on a device with Lch=5μm and Ld=80μm. Devices are fabricated with circular and linear gate, and the linear ones show worse trapping effects and larger leakage current. This might attribute to dry-etch induced defects on the sidewalls of the isolation trench.

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