由於無線網路的日漸發展，人們為了追求更高品質的網際網路而發展出無線都會網路(Wimax)。它不僅改善了無線區域網路(WLAN)距離不足的缺點，且能取代有線網路之佈線架構，使得無線網路達到另一個新的時代。

在本論文中，我們設計與實作一個符合IEEE 802.16 2004規格 Outter Receiver 之處理器，首先從理論介紹開始，說明在802.16 2004規格中所定義之各方塊，並以電路設計為目的將理論介紹之各演算法化簡與推導，接著再以matlab模擬所設計之架構，並針對解調器與解碼器作改良，以節省硬體資源，接著再以VHDL語言進行電路設計與實現，最後利用FPGA實驗版驗証所實現之電路的正確性。

在硬體設計方面，我們以較新的解調器與解碼器之方法來實現電路，以機率的方式，在解調的過程中，輸出等同於metric的機率值，送入解碼器完成soft-decision的解碼，其目的在於可減少在硬體實做上面積的需求，並且在速度上亦有著不錯的表現，而所節省之部分，可用於增加sliding window size的大小，以提高其解碼能力。至於而各方面的取捨，則由使用者的需求可有所改變。

Because of the expansion in the wireless communication system, peoples develop Worldwide Interoperability for Microwave Access (Wimax) in order to achieve higher quality of internet. It not only improved the shortcoming of distance constraint in wireless local area network (WLAN), but also substituted for the wiring structure of wired network.

This thesis focused on the design and implementation of an outer receiver processor based on IEEE 802.16 2004 specification. First, we explain the theory of every defining block in 802.16 2004, and derive pertinent algorithm for each block in order for later circuit design. Then we improve the decoder and demodulation structure to save the cost of hardware. The proposed outer receiver system is first simulated with matlab and VHDL. Finally we verify its correctness in FPGA.

The decoder and demodulation are implemented with a new method. In the procedure of demodulation, the demodulator outputs the probability values instead of 0s and 1s which act like the metric values and can be used directly in the following soft-decision viterbi decoder. Therefore, it can save the hardware cost of metric computation in viterbi decoder while maintains acceptable processing speed. As a result, we can increase the sliding window size to improve the error-correction ability on user’s demand.

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