掃描串列的發明使得邏輯電路的測試及錯誤診斷變得容易且準確，但隨著積體電路製程的進步，錯誤或瑕疵發生在掃描串列上的機率開始增加，甚至有的晶片當中掃描串列的錯誤就高達50%以上，這使得掃描串列本身的測試及錯誤診斷變得逐漸重要。
我們經由觀察之後提出一個以「訊號分布機率」為基準的新穎診斷方法來解決這令人困擾的掃描串列診斷問題，利用功能性的輸入模版代替自動測試產生的輸入模版，並且導入統計的概念，掃描出每個掃描串列單元中的值並計算該單元上所產生過的訊號一的機率，依照掃描串列順序得到一個訊號機率分布之後，再利用一些訊號處理的方式得到診斷的結果。
我們利用四個電路來測試所提出的演算法，分別是：〈1〉Montgomery Inverse電路，〈2〉單精度管線化浮點數運算單元，〈3〉有限脈衝響應濾波器，與〈4〉Viterbi解密電路。實驗結果顯示，我們所提出來的演算法對於固接錯誤、變遷錯物以及橋接錯誤都有90%以上的診斷準確率，並且如實驗數據所示，我們所提出來的診斷方法對於同樣一個電路，無論是何種錯誤，診斷所花費的時間並不會因為錯誤的數目增加而增加。這個診斷方法也適用於各種現有的錯誤模型上而且只需要極短暫的時間。

In this thesis, we investigate the scan chain diagnosis problem. A new method based on the concept of signal profiling is proposed to accurately pinpoint the location of faulty flip-flops in a scan chain. As compared to the conventional cause-effect or effect-cause analysis, this approach is much more computationally efficient because it does not have to enumerate the behaviors of a large number of fault candidates. Furthermore, it is robust and applicable to various fault types because it does not assume any specific fault model. Experimental results indicate that this approach can instantly catch flip-flop faults within a scan chain quite accurately in most cases.

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