近年來，隨著科技的快速進步，先進封裝技術變得日益重要。在這些設計中，基板佈線在確保封裝的正常運作和性能方面起著關鍵作用。雖然現有的演算法和自動佈線工具可用於幫助設計師解決佈線問題，但由於工業設計的複雜約束和規格，它們通常表現不佳，例如開路、短路、密集佈線區域和佈線迂迴。因此，佈線設計師經常需要手動修改這些結果，但這是一個耗時的過程，可能需要數週的時間才能完成。本研究提出了一種結合基於規則和人工智慧的混合式精進方法，以改善工業級覆晶球柵陣列 (Flip-Chip Ball Grid Array) 基板設計的自動佈線結果中的區域分佈和迂迴佈線現象。其主要目標是減少手動修改所需的時間。實驗結果顯示，所提出的方法能夠有效改善迂迴佈線現象和區域分佈，平均改進幅度分別達到 55% 和 32%。此外，相較於手動修改，修改所需的時間也大幅縮短，從數週減少到幾分鐘。

Advanced packaging technologies have gained significant importance in recent years due to rapid technological advancements. In these designs, substrate routing plays a critical role in ensuring the proper functioning and performance of the package. While existing works and automatic routing tools are available to assist designers in solving routing problems, they often underperform due to the complex constraints and specifications of industrial designs, such as open/short nets, dense routing areas, and routing detours. As a result, designers are frequently required to manually modify these results, which is a time-consuming process that can take weeks to complete. In this work, a hybrid refinement strategy that combines rule-based and Artificial Intelligence (AI)-based approaches to improve the area distribution and reduce detours in the auto-routing results of industrial Flip-Chip Ball Grid Array (FCBGA) substrate design is proposed, with the goal of reducing the time required for manual modifications. Experimental results demonstrate that the proposed methods effectively improve both detours and area distribution, achieving an average improvement of 55% and 32%, respectively. Furthermore, the time required for modifications is also drastically reduced from weeks to minutes.

[1] W.-H. Lai, P. Yang, I. Hu, T.-W. Liao, K. Y. Chen, D. Tarng, and C. P. Hung, “A Comparative Study of 2.5D and Fan-out Chip on Substrate: Chip First and Chip Last,” IEEE 70th Electronic Components and Technology Conference (ECTC), 2020.
[2] C.-F. Tseng, C.-S. Liu, C.-H. Wu, and D. Yu, “InFO (Wafer Level Integrated Fan-Out) Technology,” IEEE 66th Electronic Components and Technology Conference (ECTC), 2016.
[3] H.-Y. Chang, H.-M. Chen, Y.-C. Kuo, H.-T. Tsai, S. Y.-H. Chen, J.-R. Jiang, Y.-Y. Chien, and Y.-Y. Chen, “Irregular Bumps Design Planning for Modern Ball Grid Array Packages,” IEEE 70th Electronic Components and Technology Conference (ECTC), 2020.
[4] S.-T. Lin, H.-H. Wang, C.-Y. Kuo, Y. Chen, and Y.-L. Li, “A Complete PCB Routing Methodology with Concurrent Hierarchical Routing,” 58th ACM/IEEE Design Automation Conference (DAC), 2021.
[5] T.-C. Lin, D. Merrill, Y.-Y.Wu, C. Holtz, and C.-K. Cheng, “A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pair,” 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021.
[6] H.-Y. Chi, S. Y.-H. Chen, H.-M. Chen, C.-N. Liu, Y.-C. Kuo, Y.-H. Chang, and K.-H. Ho, “Practical Substrate Design Considering Symmetrical and Shielding Routes,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022.
[7] Y. He and F. S. Bao, “Circuit Routing Using Monte Carlo Tree Search and Deep Neural Networks,” arXiv:2006.13607, 2020.
[8] Y. He, H. Li, T. Jin, and F. S. Bao, “Circuit Routing Using Monte Carlo Tree Search and Deep Reinforcement Learning,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2022.
[9] Y.-H. Yeh, S. Y.-H. Chen, H.-M. Chen, D.-Y. Tu, G.-Q. Fang, Y.-C. Kuo, and O.-Y. Chen, “DPRoute: Deep Learning Framework for Package Routing,” 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 2023.
[10] S. Liu, G. Chen, T. T. Jing, L. He, R. Dutta, and X.-L. Hong, “Effective Congestion Reduction for IC Package Substrate Routing,” ACM Transactions on Design Automation of Electronic Systems, 2010.
[11] Y.-H. Yeh, S. Y.-H. Chen, H.-M. Chen, D.-Y. Tu, G.-Q. Fang, Y.-C. Kuo, and P.-Y. Chen, “Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2022.
[12] “PingoLH/CenterNet-HarDNet: Object detection achieving 44.3 mAP / 45 fps on COCO dataset,” https://github.com/PingoLH/CenterNet-HarDNet.
[13] K. Duan, S. Bai, L. Xie, H. Qi, Q. Huang, and Q. Tian, “CenterNet: Keypoint Triplets for Object Detection,” IEEE/CVF International Conference on Computer Vision (ICCV), 2019.
[14] P. Chao, C.-Y. Kao, Y.-S. Ruan, C.-H. Huang, and Y.-L. Lin, “HarDNet: A Low Memory Traffic Network,” IEEE/CVF International Conference on Computer Vision (ICCV), 2019.
[15] K. He, X. Zhang, S. Ren, and J. Sun, “Deep Residual Learning for Image Recognition,” IEEE/CVF Computer Vision and Pattern Recognition Conference (CVPR), 2016.