This thesis proposed the design techniques to achieve high-performance, fully-integration, and area-efficient optoelectronic ICs (OEICs) for high-speed optical communication and wide-dynamic rage image sensing. The design concepts were demonstrated by three 10 Gb/s optical receiver analog front-ends and a wide-dynamic range unit pixel readout circuit, both realized in a commercial 0.35 um SiGe BiCMOS process. The results presented superior performances compared with other published literatures.
The three proposed broadband techniques are: 1. The capacitive emitter degeneration (CED) generates a zero to compensate the dominate pole of transimpedance amplifier (TIA) and a higher frequency pole to increase the bandwidth; 2. The input parasitic capacitance immunization (IPCI) technique provides a negative capacitance of -0.158 pF to reduce the input parasitic capacitance to enhance the bandwidth by a factor of 1.64; 3. The improved input parasitic capacitance immunization (IIPCI) technique provides larger negative capacitance of -0.426 pF than the IPCI technique by a factor of 2.7 to strongly diminish the total input capacitance of TIA without affecting transimpedance gain. The achieved transimpedance gains and bandwidths for the TIAs with the three techniques are (101 dBohm, 6.4 GHz), (104 dBohm, 7.2 GHz), and (107.3 dBohm, 8.85 GHz), respectively. These techniques were used to enhance the gain-bandwidth performance of TIAs without using large-area inductor peaking or passive matching network under a large input capacitance load.The designed 10 Gb/s optical receiver analog front-ends also utilized high performance differential active Miller capacitor (DAMC) circuits to eliminate the need of off-chip capacitors so as to achieve area-efficient design. The fully integrated design can avoid off-chip noise interference. The measured results showed very precise crossing points (49.1%, 50.1%, and 50.5%, respectively) and minimal dc offset, defined at a bit-error-rate (BER) of 10-12 using the 231-1 pseudorandom bit sequence pattern.
In this thesis, the feasibility of integrating on-chip photodetectors was also explored. Monolithically integrated SiGe BC diode which exhibits high responsivity has been realized without altering any process step. For visible light applications, we used the SiGe BC diode to form the pixel elements of imager, which achieves a measured wide input dynamic range of 153.4 dB (0.01 lx to 470000 lx). For high-speed optical communication, the proposed optical receiver employing a SiGe BC diode attains a data rate of 3.2 Gb/s.

本論文針對10 Gb/s光纖通訊系統和高動態影像感測提出創新設計技巧，以期達到高效能光電積體電路之設計。這些設計概念分別以3組10 Gb/s的光纖接收前端電路和高動態範圍單一像素讀出電路來展示，並且以標準的0.35 um SiGe BiCMOS製程來實現這些積體電路，實驗結果呈現出來的電路效能皆優於目前文獻。
針對光纖接收前端電路提出的寬頻技巧分別為：以電容性射極回授阻抗(Capacitive Emitter Degeneration，CED)產生一個零點來補償轉阻放大器(Transimpedance Amplifier, TIA)的主極點，同時產生一較高的極點來增加電路頻寬。以輸入寄生電容消除(Input Parasitic Capacitance Immunization, IPCI)技術產生等效負電容(-0.158 pF)來降低TIA之輸入寄生電容，進而將頻寬增加1.64倍。以改良型輸入寄生電容消除(Improved Input Parasitic Capacitance Immunization, IIPCI)技術可產生更大的等效負電容(-0.426 pF) ，此負電容效應比IPCI增強了2.7倍之多，可用來更有效率的增加頻寬且不影響TIA的增益。整體轉阻增益和頻寬分別可達到(101 dBohm, 6.4 GHz)、 (104 dBohm, 7.2 GHz) 、和(107.3 dBohm, 8.85 GHz)。再較大的輸入電容負載之下，這些設計技巧不需使用到大面積的電感或被動式的匹配網路就可增強TIAs的增益頻寬特性。
在所設計的10 Gb/s光纖接收前端電路中，使用差動主動米勒電容(Differential Active Miller Capacitor, DAMC)電路來取代外接式電容可更有效率的使用晶片面積，而此全整合性的設計也可避免掉晶片外部的雜訊干擾，由量測結果可得到，在使用231-1的虛擬隨機位元序列(Pseudorandom Bit Sequence, PRBS)以及誤碼率(Bit-Error-Rate, BER)為10-12的測試條件之下，可得到相當精確的交錯點(分別為49.1%，50.1%，和50.5%)以及最小化的直流偏移量。
在不更改製程步驟下實現全整合型的SiGe 基集接面二極體(SiGe BC Diode) ，其具備高光響應度(Photoresponsivity)特性，在可見光波段的應用上，我們使用此SiGe BC diode來設計影像偵測器的像素電路，量測結果可得到高達153.4 dB(0.01 lx to 470000 lx)的光輸入動態範圍。在高速光纖通訊應用上，以SiGe BC diode整合所提出的光纖接收電路，其操作速度可達到3.2 Gb/s。

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