晶片網路已成為有效降低多核心晶片溝通負擔的利器，並廣泛使用於提升平行程式之效能。若要更加提升程式效能，則需多核心晶片網路效能之評估，針對程式選擇適當之晶片網路。追蹤檔驅動模擬為一快速方便之晶片網路評估方式，然其模擬需要曠日廢時地產生各種不同核心數之追蹤檔，大大降低評估效率。故為了增進晶片網路評估效率，於此篇碩士論文提出快速追蹤檔重製。追蹤檔重製為透過觀察追蹤檔中核心溝通模式探討程式行為，並根據此程式行為製造出符合程式語意之追蹤檔。實驗證實，追蹤檔重製能確實反映趨勢且適用於晶片網路評估，故使追蹤檔驅動模擬更加輕鬆便利。

[1] L.Benini and G.D.Micheli, “Networks on chips: A soc paradigm,” IEEE Computers, vol. 1, pp. 70–78, Jan 2002.
[2] J. Hestness, et al., “Netrace: dependency-driven trace-based network-on-chip simulation,” In Proceedings of the Third International Workshop on Network on Chip Architectures. ACM, New York, NY, USA, 2010, pp. 31–36.
[3] C. Nitta, K. Macdonald, M. Farrens, and V. Akella. Inferring packet dependencies to improve trace based simulation of on-chip networks. In Networks-on-Chip (NOCS), 2011 FifthACM/IEEE International Symposium on (to appear), May 2011.
[4] Hsiang-Wei Lo, “Causality-aware intermediate representation for trace-driven simulation of network-on-chip”, Master Thesis, Department of Computer Science, National TsingHua University, Hsinchu, Taiwan 30013, R.O.C., July 2011.
[5] Cher-Shan Yee, “A Trace Synthesis Tool for Trace-Driven Simulators of Network on Chip”, Master Thesis, Department of Computer Science, National TsingHua University, Hsinchu, Taiwan 30013, R.O.C., July 2011.
[6] Yoshi Shih-Chieh Huang, Yu-Chi Chang, Tsung-Chan Tsai, Yuan-Ying Chang, and Chung-Ta King. 2012. “Attackboard: a novel dependency-aware traffic generator for exploring NoC design space.” In Proceedings of the 49th Annual Design Automation Conference (DAC '12). ACM, New York, NY, USA, 376-381