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研究生： 楊竣宇
Yang, Jun-Yu
論文名稱： 具有製程適應能力以及支援從容退化之線上失效監控技術之容錯型鎖延遲迴路電路設計
Process-Resilient Fault-Tolerant DLL Design with Failure Monitor to Support Graceful Degradation
指導教授： 黃錫瑜
Huang, Shi-Yu
口試委員: 吳誠文
Wu, Cheng-Wen
李昆忠
Lee, Kuen-Jong
洪浩喬
Hong, Hao-Chiao
黃俊郎
Huang, Jiun-Lang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 58
中文關鍵詞： 鎖延遲迴路 、容錯 、軟錯誤 、相位誤差 、監控器
外文關鍵詞： Delay-Locked Loop, Fault-Tolerant, Soft Error, Phase Error, Monitor
相關次數： 點閱：2  下載：0 
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    • 一個應用於安全關鍵的IC中，通常都會要求”零故障率”和長達10年以上的使用壽命。為了實現”零故障率”的目標，通常會採以兩道防線來做防護，第一防線採用容錯(Fault and Soft-Error Tolerance)方法，而第二防線則須要採從容退化(Graceful Degradation)的機制。在本論文中，提出一個具有容錯的鎖延遲迴路電路設計作為第一道防線，其中顯示單純地使用三重模塊冗餘(Triple Module Redundancy)技術將會使鎖延遲迴路無效，除非採用簡單而強大的靜態時序校正方法來消除由表決電路引起的延遲效應。除此之外，我們更進一步地採用動態時序校正方法對其增強，以使整體性能不受製程變異的影響。透過提出的方法，一個鎖延遲迴路在1000個時脈週期內的最大相位誤差，可以從僅使用三重模塊冗餘技術的130皮秒大幅降低至採用靜態時序校正方法的20皮秒，接著再進一步透過動態時序校正方法降低至11皮秒。
    此外，我們也將從容退化機制視為容錯型鎖延遲迴路(FET-DLL)的第二道防線。如此一來，當容錯型鎖延遲迴路的容錯能力下降時，可以藉由一種新穎且低成本的過量相位誤差檢測器來監控，使它不會盲目地運行。在監控過程中，任何超出預先學習之相位誤差容忍範圍的相位，都將觸發故障警報以回報錯誤。該檢測器還可用於支援在線測試，以確定一個基於TMR的FET-DLL中，是否存在故障的模塊。我們以90nm CMOS製程實現所提出的方法，結果顯示該相位誤差檢測器的面積僅有60umx60um=0.0036mm2，只佔整個FET-DLL面積的4.12％。

    In an IC used for safety-critical applications often demands almost “zero failure rate” and a long lifetime of more than 10 years. To achieve this grand challenge, a Fault and Soft-Error Tolerant (FET) scheme is often desirable for the first line of defense and a graceful degradation scheme as the second line of defense. In this thesis, we first present a process-resilient FET-DLL design as the first line of defense. We will first show that a naïve Triple-Module Redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles in DLL can be reduced tremendously from 130ps using only naïve TMR to 20ps using static timing correction, and then further down to 11ps using the dynamic timing correction.
    Also, we consider a graceful degradation scheme as the second line of defense for an FET-DLL. By doing so, a FET-DLL will not operate blindly when its tolerance to faults or soft errors has been degraded. This is achieved by incorporating a novel low-cost excessive phase-error monitor. Any excessive phase error beyond a pre-learned phase-error tolerance range will trigger an alarm of failure. This monitor can also be used to support an online test for deciding whether there is a faulty module in our TMR-based FET-DLL at any given time. We have implemented the proposed scheme in a 90nm CMOS process. The results show that the area of this excessive phase error monitor is as small as 60umx60um=0.0036mm2, or only 4.12% of the entire FET DLL.

    Abstract i 摘要 ii 誌謝 iii Content iv List of Figures vi List of Tables viii Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Thesis Organization 4 Chapter 2 Preliminaries 5 2.1 The Role of a DLL for Clock Synchronization 5 2.2 Basics of a DLL 6 Chapter 3 Proposed Fault and Soft-Error Tolerance Scheme for DLL 9 3.1 Naïve FET-DLL Architecture using TMR 9 3.2 FET-DLL with Static Timing Correction Scheme 12 3.3 FET-DLL with Dynamic Timing Correction Scheme 16 Chapter 4 Experimental Results of FET-DLL 27 4.1 FET-DLL with Static Timing Correction 27 4.2 FET-DLL with Dynamic Timing Correction 31 Chapter 5 Proposed Monitoring Scheme for FET-DLL 37 5.1 Basic Principle 37 5.2 Basic Building Block – Phase-Error Checker 37 5.3 Circuit for the Differential Pair of Delay Lines 42 5.4 Operation of Failure Monitor 44 5.5 Application to Module-level Testing 46 Chapter 6 Experimental Results of FET-DLL with Failure Monitor 49 6.1 Layout and Characterization of PE Checker 49 6.2 Layout of FET-DLL with failure monitor 50 6.3 Post-Layout Simulation Results 51 Chapter 7 Conclusion and Future Work 54 7.1 Conclusion 54 7.2 Future Work 55 References 56

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