研究生: |
郭家祺 Kuo, Chia Chi |
---|---|
論文名稱: |
可應用於紅外線感測器之擁有固定圖像雜訊消除及感光區間調變的脈衝寬度調變高動態範圍讀出電路 A High Dynamic Range Pulse Width Modulation Readout IC with Fixed Pattern Noise Reduction and Sensitive Range Tuning for IR Focal Plane Arrays |
指導教授: |
謝志成
Hsieh, Chih Cheng |
口試委員: |
邱進峯
陳柏宏 陳新 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 英文 |
論文頁數: | 70 |
中文關鍵詞: | 高動態範圍 、脈衝寬度調變 、電容跨組抗放大器 、紅外線交平面陣列 、影像感測器 |
外文關鍵詞: | HDR, PWM, CTIA, IRFPA, Image sensor |
相關次數: | 點閱:1 下載:0 |
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本論文提出一個可應用於紅外線感測器(IR Focal Plane Arrays)與需要固定偏壓感測元件的脈衝寬度調變(Pulse Width Modulation)讀出電路,具有良好功率消耗(Good Power Efficiency)與高動態範圍(High Dynamic Range)特性,並達成固定圖像雜訊消除(Fixed Pattern Noise Reduction)與感光區間調變(Sensitive Range Tuning)功能。
為了達到良好的功率消耗表現,本論文所提出的電容反饋跨阻抗放大器(Capacitive Trans-impedance Amplifier)配合脈衝寬度調變讀出電路,將操作電壓由傳統紅外線感測器的3.3伏特降至1.5伏特。並且在曝光操作上使用了雙重曝光延續計算(Dual-Exposure Extended-Counting)技巧,成功克服傳統脈衝寬度調變讀出感測器,其曝光時間受到操作方式限制的問題。除了動態範圍延展,好的影像品質也必須兼具,因此在電路中利用耦合電容,實作出自動歸零與偏移電壓消除(Auto Zeroing & Offset Cancellation)機制來消除固定圖像雜訊。另外提出一個時間控制自動對其斜坡電壓(Aligned Time-Control Ramp)產生器,提供一個可調變斜率的閥值電壓(Threshold Voltage)供給脈衝寬度調變操作,達成感光區間調整的功能。
為驗證本電路,此架構使用0.18微米1P6M互補式金氧半導體製程製作,晶片總面積為1700×1800μm2,擁有64X64像素陣列並搭載上述構想的讀出電路原型,操作於類比端1.5伏特,數位端0.8伏特電壓下。量測驗證成果,此提出的高動態範圍讀出電路架構達到132dB的動態範圍,成功降低固定圖像雜訊至0.24%rms,230張的每秒顯示幀數,同時擁有1.27nW/frame ∙ pixel的功率消耗表現。
This thesis presents a good power efficiency and high dynamic range (HDR) Readout IC with pulse width modulation (PWM) for infrared focal plane arrays (IRFPAs) and the fixed bias needed sensors. The fixed pattern noise (PFN) reduction has been implemented and the sensitive range tuning function is available.
To achieve good power efficiency, the proposed capacitive trans-impedance amplifier (CTIA) with PWM readout circuit lower the operating voltage from 3.3V of conventional IR sensor to 1.5V. The operation of dual-exposure extended-counting (DEEC) exposure control overcome the limited exposure time issue of conventional PWM imager. Beside the dynamic range extension, fine image quality is also required. Hence, in order to implement the auto zeroing & offset cancellation (AZOC) mechanism, a coupling capacitance is added on the readout circuit to eliminate the FPN. Aligned time-control ramp (ATCR) generator is also developed and provides a tunable slope ramp threshold voltage for PWM readout operation which can achieve the sensitive range tuning function.
A prototype of 64×64 pixel imager employed these schemes has been designed and fabricated in 0.18um 1P6M CMOS technology with a chip area of 1700×1800μm2, operating under 1.5V for analog and 0.8V for digital. The measurement result shows the proposed HDR ROIC achieves 132dB dynamic range, below 0.24%rms FPN performance, 230fps frame rate and resulting 1.27nW/frame ∙ pixel power efficiency.
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