FinFET邏輯閘之佈局以減少寄生電容電阻的影響

簡易檢索 / 詳目顯示

回結果列表

研究生：	陳冠綸 Chen, Guan Lun
論文名稱：	FinFET邏輯閘之佈局以減少寄生電容電阻的影響 Exploring FinFET Cell Layout to Minimize Parasitic Impacts
指導教授：	張彌彰 Chang, Mi Change
口試委員:	連振炘 Lien, Chen Hsin 除永珍 Hsu, Yung Jane
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2016
畢業學年度：	104
語文別：	英文
論文頁數：	80
中文關鍵詞：	鰭式電晶體、寄生電阻、寄生電容、佈局、邏輯閘
外文關鍵詞：	FinFET, Parasitic resistance, Parasitic capacitance, Layout, Logic gate
相關次數：	點閱：5 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

隨著半導體最小線寬縮小到奈米尺度的今日，場效電晶體的源極和汲極越來越接近，使得閥極沒有辦法完全控制通道開關，導致即使是在閥極接地的情況下也有顯著的漏電流產生。為了解決電晶體的漏電問題，科學家們提出了鰭式電晶體(FinFET)結構來增強通道的控制能力，然而FinFET的三維結構卻帶來了多餘且顯著的寄生電阻電容，這些都會對電路造成很大的影響。為了瞭解寄生電阻電容造成影響的主要因素，我們採用非對稱的FinFET模型去模擬分析。模擬結果顯示寄生電阻與電容會在源極和汲極兩端產生不同程度的影響。藉由這個結果，我們仔細研究了FinFET佈局並提出了兩種方法去減少寄生電阻對電路的影響。一個是把源極和汲極的VIA0移到中間，另一個則是增加兩極VIA0的數量，兩種方式都經過實際下線驗證成功。此外，我們也研究了非對稱FinFET佈局面積與電路效能之間的關係，不過由於佈局規定上的限制，並沒有下線做更進一步驗證與分析。

As the feature size of the semiconductor technology shrunk to nanometer scale, the distance between source and drain of a MOSFET becomes so short such that the gate lose full control of the channel, and thus there is significant leakage current even when gate is grounded. FinFET technology has been adopted to solve this leakage problem. However, FinFET’s 3D structure incorporates significant parasitic capacitance and resistance and that can have larger impacts on circuit performance. To study the dominating factor of the impacts, asymmetric FinFET transistors have been constructed and simulated extensively. It confirms that parasitic resistance and capacitance contribute differently for the source drain terminals. Using this information, the FinFET gate layout is reviewed and two approaches to reduce the parasitic resistance impacts are proposed. One is move the VIA0 position to the center and the other is to increase the number of VIA0. Both approaches were verified by silicon test chips. Asymmetric FinFET transistor layouts that can trade off performance and area have also been developed. However, due to design rule constraints these layouts have not been verified.

摘要    I
Abstract    II
誌謝    III
Table of Content    V
List of Figures    VII
List of Tables    X
Chapter 1  Introduction    1
1 Background and Motivation    1
2 Thesis Organization    2
Chapter 2 Parasitic Resistance and Capacitance Impacts on FinFET Gates    3
1 Simulation Setup    3
2 Source and drain resistance    4
2.1 DC Analysis    4
2.2 Transient Analysis    7
2.2.1 Inverter Chain    7
2.2.2 ND2 Gate    9
2.2.3 Pass and Transmission Gates    14
3 Parasitic Capacitance    19
3.1 Transient Analysis    19
3.1.1 INV    20
3.1.2 ND2 Gate    20
4 Summary    27
Chapter 3 FinFET Layout and Parasitic RC    28
1 FinFET Structures and Layouts    28
1.1 FinFET layout    29
1.2 Layout constraints    30
2 Parasitic Capacitance    31
2.1 Larger fingers Layout    32
2.1.1 INV    33
2.1.2 NAND2 gate    39
3 FinFET source /drain parasitic resistor model    43
3.1 Impacts of VIA0 location    43
3.2 Impacts of VIA0 number    45
3.3 Impacts on larger fins structure    46
3.4 Current sensitivity of S/D parasitic resistance    47
3.5 Impacts on circuit performance    50
4 Summary    53
Chapter 4 Layout Modification and Silicon verification    55
1 Proposed layout Modification    55
1.1 Parasitic capacitance    56
2 Test line design    57
2.1 Ring oscillator    57
2.2 Multiple finger layouts    59
3 Silicon measurements    60
3.1 Ring oscillator    60
3.2 One finger and multiple fingers transistors    64
3.2.1 Single transistor    64
3.2.1 Inverter    71
4 Summary    73
Chapter 5 Conclusions and Future work    75
1 Conclusions    75
2 Future work    76
Reference    78


                                

[1] G. E. Moore, "Progress in digital integrated electronics," Proceedings of International Electron Devices Meeting, 1975, pp. 11-13.
[2] X. Xu, R. Wang, and J. Zhuge, "High-Performance BOI FinFETs Based on Bulk-Silicon Substrate," IEEE Translation on Electron Devices, vol. 55, no. 11, pp. 3246-3250, Nov. 2008.
[3] C. R. Manoj, Angada B. Sachid, F. Yuan, C.-Y. Chang, and V. R. Rao, "Impact of fringe capacitance on the performance of Nanoscale FinFETs," IEEE Electron Device Letters, vol. 31, no. 1, pp. 83-85, Dec. 2010.
[4] A. Redolfi, E. Sleeckx, K. Devriendt, D. Shamiryan, T. Vandeweyer, N. Horiguchi, M. Togo, J. M. D. Wouter, M. Jurczak, T. Hoffmann, A. Cockburn, V. Gravey, and D. L. Diehl, "Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques," Proceedings of 12th International Conference on Ultimate Integration on Silicon, 2011, pp. 1-3.
[5] Kelin J. Kuhn, "CMOS scaling for the 22nm node and beyond: Device physics and technology," International Symposium on VLSI Technology, Systems and Applications (VLSI- TSA), 2011, pp. 1-2.

[6] M. Alioto, "Comparative evaluation of layout Density in 3T, 4T, and MT FinFET standard cells," IEEE Translations on Very Large Scale Integration System, vol. 19, no. 5, pp. 751-762, May 2011.
[7] P. Schuddinck, "Standard cell level parasitics assessment in 20nm BPL and 14nm BFF," Proceedings of International Electron Devices Meeting, 2012, pp. 25.3.1-25.3.4.
[8] S.-Y. Wu, "A 16nm FinFET CMOS technology for mobile SoC and computing applications," Proceedings of International Electron Devices Meeting, 2013, pp. 9.1.1-9.1.4.
[9] M. Rashed, "Innovations in special constructs for standard cell libraries in sub 28nm technologies," Proceedings of International Electron Devices Meeting, 2013, pp. 248-251.
[10] N. Lu, T. B. Hook, J. B. Johnson, C. Wermer, C. Putnam, and R. A. Wachnik, "Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements," IEEE Electron Device Letters, vol. 34, no. 9, pp. 1100-1102, Sept. 2013.
[11] A. Paul, "Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-Fin SOI FINFETs," Proceedings of International Electron Devices Meeting, 2013, pp. 361-364.
[12] M.-S. Kim, T. Vandeweyer, E. Altamirano-Sanchez, H. Dekkers, E. Van Besien, and D. Tsvetanova, "Self-aligned double patterning of 1x nm FinFETs; A new device integration through the challenging Geometry," 14th International Conference on Ultimate Integration on Silicon (Ulis), 2013, pp. 102-5.
[13] P.-H. Su, Y. Li, "Design optimization of 16-nm bulk FinFET technology via geometric programming," International Workshop on Computational Electronics, 2014.
[14] A. Pandey, "Effect of load capacitance and input transition time on FinFET inverter capacitances," IEEE Translation on Electron Devices, vol. 61, no. 1, pp. 30-36, Jan. 2014.
[15] T. B. Hook, "Fully depleted devices for designers: FDSOI and FinFETs," Proceedings of IEEE Custom Integrated Circuits Conference, 2012, pp. 18-21.
[16] F.-H. Meng, P.-Y. Lin, and Y.-L. Chiu, "Effect of three-dimensional current distribution on characterizing parasitic resistance of FinFETs," Japanese Journal of Applied Physics, vol.55, no. 4S, Mar. 2016.
[17] H.-Y. Lin, "Parasitic Impacts on Sub-20nm FinFET Transistors," master thesis, NTHU, July 2016

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文