Abstract

In this thesis, the substrate coupling is discussed. The most important discussion of substrate coupling is adding TSV (Through-Silicon-Vias), which is proposed to solve the interconnect problem, to suppress substrate coupling. In order to understand the substrate coupling, different conditions are considered such as substrate concentration, substrate thickness, deep trench, the distance, metal shielding, and TSV. The Scattering parameter is used to evaluate the level of substrate coupling and the range of simulation frequency is from 107Hz to 1011Hz. We find that TSV with ground indeed suppress the substrate coupling and show the improvement of 8.3db at 109Hz and 17.3db at 1010 Hz. Therefore, TSV is really a good technique for suppressing substrate coupling.

摘要

在這篇論文，主要是探討影響基板耦合的因素，其中最重要的是要探討TSV對基板耦合的影響。TSV是為了解決未來電路連接會產生問題所提出的解決方法，有關TSV的製程會在論文中介紹。除了探討TSV，我們還會探討各種影響基板耦合的因素，包括不同基板濃度，基板厚度，發射端與接收端的距離，加入deep trench，TSV和金屬等。我們是利用S參數來判定基板耦合的難易程度，而程式模擬的頻率範圍是從107Hz到1011Hz。由模擬程式發現接地的TSV可以大大降低基板耦合量。接地的TSV分別可在109Hz 提供8.3dB和1010 Hz 提供17.3dB，因此，接地的TSV是個良好的抑制基板耦合的技巧。

[ 1 ]
Guotao Wang, Caroline Merrill, Jie-Hua Zhao, Steven K. Groothuis, and Paul S. Ho,“Packaging Effects on Reliability of Cu/Low-k Interconnects”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 3, 2003

[ 2 ]
T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffiann', K. Johnson', C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, 1. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IEDM Technical Digest. IEEE International, 2003

[ 3 ]
H.J. Osten, J.P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k Gate Dielectrics with Ultra-low Leakage Current Based on Praseodymium Oxide”, IEDM Technical Digest, 2000, pp.653 – 656

[ 4 ]
“INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2007 EDITION INTERCONNECT”, http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_Interconnect.pdf

[ 5 ]
M.I. Natarajan#, S. Thijs, D. Tremouilles, D. Linten, N. Collaert, M. Jurczak, and G. Groeseneken, “ESD protection for sub- 45 nm MugFET technology”, Proceedings of 14th IPFA, 2007

[ 6 ]
D. Trémouilles*, S. Thijs, C. Russ, J. Schneider, C. Duvvury, N. Collaert, D. Linten, M. Scholz, M. Jurczak, H. Gossner, and G. Groeseneken, “Understanding the Optimization of Sub-45nm FinFET Devices for ESD Applications”, 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007

[ 7 ]
S. Spiesshoefer and L. Schape, “IC Stacking Technology using Fine Pitch, Nanoscale through Silicon Vi”, Electronic Components and Technology Conference, 2003

[ 8 ]
Y. K. Tsui and S. W. Ricky Lee, ”Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing”, IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 3, 2005

[ 9 ]
Kenji Takahashi and Masahiro Sekiguchi, “Through Silicon Via and 3-D Wafer/Chip Stacking Technology,” Symposium on VLSI Circuits Digest of Technical Papers, 2006

[ 10 ]
Silke Spiesshoefer, Leonard Schaper, Susan Burkett, Gowtham Vangara, Ziaur Rahman, and Parthiban Arunasalam, ”Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development”, Electronic Components and Technology Conference, 2004 , pp. 466- 471

[ 11 ]
Y. K. Tsui, S. W. R. Lee, J. S. Wu, .I. K. Kim, and M. M. F. Yuen, ”Three-dimensional packaging for multi-chip module with through-the-silicon via hole”, Electronics Packaging Technology Conference, 2003

[ 12 ]
Wu, J.H.; del Alamo, J.A, “Through-Substrate Interconnects for 3-D ICs, RF Systems, and MEMS”, Silicon Monolithic Integrated Circuits in RF Systems, 2007 , pp.154 – 157

[ 13 ]
Joyce H. Wu, Jörg Scholvin, and Jesús A. del Alamo, “A Through-Wafer Interconnect in Silicon for RFICs,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, 2004

[ 14 ]
盧信嘉, “System-in-Package“, http://cc.ee.ntu.edu.tw/~leonardo/U0270/introduction.pdf

[ 15 ]
RAO TUMMALA, P. MARKONDEYA RAJ AND VENKY SUNDARAM, “Next-generation PackagingMaterials”,http://ap.pennnet.com/Articles/Article_Display.cfm?Section=Articles&Subsection=Display&ARTICLE_ID=205981

[ 16 ]
Xavier Aragon`es and Antonio Rubio, “Experimental Comparison of Substrate Noise
Coupling Using Different Wafer Types”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, 1999

[ 17 ]
吳誠文, “半導體產業推手辦公室專刊第29期”, 2007

[ 18 ]
P. R. Morrow, C.-M. Park, S. Ramanathan, M. J. Kobrinsky, and M. Harmes,” Three-Dimensional Wafer Stacking Via Cu–Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology,” IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, 2006

[ 19 ]
“EMC-3D Consortium Created for the Development of Cost-EffectiveThrough-Silicon-Via Interconnects”, http://www.semitool.com/pdf_files/EMC-3D_OVERVIEW.PDF

[ 20 ]
Peter Ra", Detlef Bonfert, Horst Gieser, Jurg Haufe*, Franz Iberl, Armin Klumpp, Andreas Kux*, and Robert Wieland, “InterChip Via Technology for Vertical System Integration”, Interconnect Technology Conference, 2001, pp.160 – 162

[ 21 ]
Dong Min Jang', Chunghyun Ryul*, Kwang Yong Lee2, Byeong Hoon Cho', Joungho Kiml*, Tae Sung Oh2, Won Jong Lee' and Jin Yu',” Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)”, Electronic Components and Technology Conference,2007

[ 22 ]
Masaya Kawano, “A 3D Packaging Technology for High-Density Stacked DRAM”,
VLSI Technology, Systems and Applications, 2007.