在本論文中，針對QC-LDPC編碼調變設計了一整套地建碼流程。首先，提出了能應用在QC-LDPC的密度演化，它能區分出相對應調變符元中不同位元的機率分布，且能在QC-LDPC碼的迭代過程中計算出機率分布的變化。傳統的密度演化只能在BPSK訊號中計算出解碼的臨界值，而QC-LDPC的密度演化可以進一步用來推估更高階層的迭代式編碼調變的解碼臨界值，及碼內結構對解碼臨界值所造成不同的影響。接著，為了要降低錯誤平層，需要利用交錯器來降低錯誤平層。對於non-Gray的迭代式編碼調變，需要利用交錯器來設法將陷入同一個短環內的變異節點分散到不同的符元中，然而在QC-LDPC碼中，我們可以利用基礎矩陣的位移指標，將矩陣中的短環找出，且將陷入短環的變異節點分散到不同的符元。因此，我們可以不必要透過交錯器而僅僅靠著基礎矩陣中的簡單地行轉換，一樣能達到降低錯誤平層的效果。我們針對適用再TLC快閃記憶體且碼長為18396，碼率是0.94的QC-LDPC迭代式編碼調變(8PAM)提出了一整套的設計流程。當使用最佳的 non-Gray mapping ，能以著較低的平均維分布而與gray mapping達到相似的性能，最後模擬也顯示，QC-LDPC編碼調變根據整套地設計流程能達到與預期一樣好的解碼臨界值與低錯誤平層，也能大幅降低解碼的複雜度。

In this theses, a design flow for coded modulation that integrates quasi-cyclic low-density parity check (QC-LDPC) codes and iterative detection and decoding (IDD) is proposed. The first major technique in this work is a modified QC-LDPC based density evolution(QCDE). It can indicate the difference between the probability distribution of bits corresponding to individual modulation level of the received symbols, and evaluate the changing of the probability distribution following the structure of the QC-LDPC codes. Comparing the conventional density evolution that can only detect the decoding threshold for BPSK signal, the modified QCDE can evaluate the decoding and detection threshold for IDD receiver with high order modulation, and the effect of the code structure can also be observed.
The second major technique is QC-LDPC-based interleaving scheme for error floor lowering. For coded modulation with non-Gray mapping and IDD, an interleaver is required in order to distribute the variable nodes in a single short cycles of QC-LDPC codes into different symbols, or high error floor will be introduced. Take the advantage of the structure of QC-LDPC code, the variable nodes in a single short cycles can be observed via the based matrix and the shift indices, and are mapped into different symbols. Therefore, the interleaver can be removed after a simple column change in the base matrix is applied.
The proposed design flow is applied to the construction of the coded modulation combining a length-18396 rate-0.94 QC-LDPC code and the 8-PAM modulation, which is suitable for TLC (triple-level cell) flash memory. Refer to the binary switching algorithm, an optimized non-Gray mapping is selected, then a similar performance can be achieved using a QC-LDPC code with a much smaller degree distribution comparing to that combing the Gray mapping. It shows that, except the low decoding/detection threshold and low error floor, the coded modulation designed using the proposed design flow also has a much low decoding complexity.

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