卷積神經網絡（CNN）在圖像分類、去噪和物體檢測方面具有高度的有
效性，但其計算效率可以通過加速器顯著提升。傳統加速器通常採用固定
的資料流，這可能並不適合所有的卷積神經網絡層。1-D PE 陣列架構支持
靈活的資料流，但其可擴展性仍然是一個重大問題。此外，目前的設計空
間探索（DSE）工具主要關注 2D 網格 PE 陣列或脈動陣列架構，忽略了對
一維處理單元陣列的晶片上網絡（NoC）架構的探索。這些工具也缺乏對每
層可重構資料流和塊大小的支持，並且通常需要將 DNN 模型重寫為特定配
設定檔格式，這既不方便也效率低下。
為了解決這些限制，我們提出了一種基於 SystemC 並集成 TVM 的新型
晶片上網路一維處理單元陣列模擬器。我們的模擬器支持靈活的資料流和
塊大小配置，從而實現對神經網路模型的高效性能估計。晶片上網絡架構
允許各種尺寸和形狀的設定，提供近乎週期精確的性能估計模型。通過添
加自定義 Opstrategy、自定義 compute 和自定義 C runtime，TVM 與晶片上
網絡模擬器集成，自動化性能估計過程，優化每層的切片和資料流策略。
此方法支援各種神經網路開發框架，增強了所提方法的可用性和效率。
實驗結果證明了我們方法的有效性，顯示出相較於現有工具如 Scalesim
[1] 的 1.84 倍加速。我們的模擬器評估了 VGG16 上不同資料流和塊大小的
性能，在延遲和資源利用率方面取得了顯著改進。所提方法為 DNN 加速器
設計提供了一種可擴展且靈活的解決方案，解決了現有方法的不足之處。

Convolutional Neural Networks (CNNs) are highly effective for image classi-fication [2], denoising [?, ?] and object detection [3], but their computational efficiency can be significantly enhanced using accelerators. Traditional accelerators often employ fixed dataflows, which may not be optimal for all CNN layers. The 1-D PE array architecture supports flexible dataflows, but scalability remains a significant issue. Moreover, current Design Space Exploration (DSE) tools focus on 2D-mesh PE arrays or systolic array architectures, neglecting the exploration of Network-on-Chip (NoC) architectures for 1-D PE arrays. These tools also lack support for reconfigurable dataflows and tile sizes per layer, often requiring the rewriting of DNN models into specific configurations, which is both inconvenient and inefficient.
To address these limitations, we propose a novel NoC-based 1-D PE array simulator based on SystemC integrated with TVM. Our simulator supports flexible dataflow and tile size configurations, enabling efficient performance estimation for DNN models. The NoC architecture allows for various sizes and shapes of configurations, providing a nearly cycle-accurate model for performance estimation. By adding custom Opstrategy, custom compute, and custom C runtime, TVM is integrated with the NoC simulator to automate the performance estimation process, optimizing tiling and dataflow strategies for each layer. This integration supports various DNN frameworks, enhancing the usability and efficiency of the proposed method.
Experimental results demonstrate the effectiveness of our approach, showing a 1.84x speedup compared to existing tools like Scalesim [1]. Our simulator evaluates the performance of different dataflows and tile sizes on VGG16, achieving significant improvements in latency and resource utilization. The proposed method offers a scalable and flexible solution for DNN accelerator design, addressing the shortcomings of existing approaches.

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