A General Purpose Elastic Buffer Design for Asynchronous Circuit Applications

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研究生：	陳禹安 Chen, Yu-An
論文名稱：	A General Purpose Elastic Buffer Design for Asynchronous Circuit Applications 多用途彈性緩衝器設計於非同步電路應用
指導教授：	張彌彰 Chang, Mi-Chang
口試委員:	馬席彬 Ma, Hsi-Pin 郭治群 Guo, Jyh-Chyurn
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	96
中文關鍵詞：	非同步電路、異步電路、非同步管線、彈性緩衝器、先進先出、超大型積體電路
外文關鍵詞：	Asynchronous circuit, clockless circuit, Asynchronous pipeline, Elastic Buffer, FIFO, VLSI
相關次數：	點閱：1 下載：0
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因為非同步電路不需使用共同時脈同步，因此當輸出可以傳遞至準備好的下一級時，就可以執行運算。執行運算所需的時間通常取決於輸入樣本，也因為不需要同步，所以執行時間通常少於最長路徑的延遲時間。若擷取輸入樣本與傳遞輸出結果至下一級不需要延遲時間，則非同步電路可以達到平均延遲的效能，而取代同步電路的時脈週期所採用最糟情況延遲。
當電路準備好執行但輸入無法提供有效資料時，電路必須等待，此種情況稱為飢餓；當電路無法傳遞輸出至下一級時，電路又必須等待，此種情況稱為阻塞。不論是飢餓或是阻塞情況，都會降低非同步電路的產出量。在每一級中間插入緩衝器，可以盡量減少飢餓和阻塞的情況，從而提高非同步電路的產出量。
本篇論文提出一種多功能彈性緩衝器應用於非同步電路，且可以操作於兩相及四相交握協定。其縮放資料匯流排與緩衝器深度的大小利用可重複使用區塊而容易實現，且不需要重新設計電路架構。彈性緩衝器利用客製化的C元件、並行的控制訊號與環狀架構來實現彈性緩衝器，使其擁有較好的面積與效能。
電路模擬於65-nm TSMC製程，操作電壓為1.2V且工作在25℃環境下。儲存運作時間為69.5ps，且獲取運作時間為174.6ps。當彈性緩衝器為空狀態時，資料可以直接穿越彈性緩衝器，而運作時間為348.8ps。當彈性緩衝器為滿狀態時，前一級儲存資料時會需要一段反應時間，其運作時間為386.5ps。
為了驗證彈性緩衝器與量測效能，我們設計了自我運做電路 (SRC)，且完成不同運算延遲與緩衝器深度的模擬。模擬的產出量相當符合公式的預測，且彈性緩衝器可以提升相依於運算延遲分佈的非同步管線產出量約11%~59%.

Asynchronous circuits need no synchronization. Thus they can perform designated operation once the inputs are available, and the output can be delivered to the next stage when it is ready. The time needed to perform an operation is usually input pattern dependent. Due to no need of synchronization, the operation time is usually less than the longest path delay. If there is no delay in obtaining input patterns and in delivering results to the next stage, the asynchronous circuit can achieve average-delay performance, instead of worst-case delay that synchronous circuits must assume.
In the case that the input cannot be supplied when the circuit is ready, the circuit must wait. This situation is called starvation. In the case that the output cannot be delivered to the next stage, the circuit also needs to wait. This is called blocking. Either starvation or blocking reduces the asynchronous circuit’s throughput. A buffer can be inserted in-between these stages to minimize the starvation and blocking and hence increase the asynchronous circuit throughput.
In thesis, we present a general purpose Elastic Buffer for asynchronous circuit application. It works with both two-phase and four-phase handshaking protocols. The data bus width and the buffer depth can be easily scaled. The Elastic Buffer is implemented with custom C-elements, with parallel control signals and circular architecture for better area efficiency and performance.
Using TSMC 65LP technology at 1.2V and 25℃.The store operation of the Elastic Buffer takes 69.5ps, fetch takes 174.6ps. Our Elastic Buffer also has a pass-through mode, which allows data to deliver to the next stage directly when buffer is empty. The pass-through operation takes 348.8ps. When the buffer is full, then the next data will need to wait until a slot is becoming available. The waiting time is called response time. The shortest response time is 386.5ps in our design.
In order to verify our Elastic Buffer and measure the performance, we design a Self Run Circuit (SRC). More simulations with different operation delays and buffer depths are performed. The simulated throughputs match with the formula prediction, and we showed that with the Elastic Buffer the asynchronous pipeline throughput can be improved from 11% to 59% depends on the operation delay distribution.

摘     要    i
Abstract    ii
誌     謝    iv
Contents    v
List of Figures    ix
List of Tables    xiv
Chapter 1 Introduction    1
1 Background    1
2 Motivation    2
3 Organization    3
Chapter 2 Asynchronous Pipelined Circuits and Elastic Buffers in VLSI systems    4
1 Asynchronous Pipelined Circuits    4
1.1 Handshaking Protocols    5
1.2 Bundled-Data and Data Encoding    6
1.3 Muller C-element    9
1.4 Muller Pipelined Circuits    10
1.5 MOUSETRAP Pipelined Circuits    12
2 Throughput and Asynchronous Pipeline Stalls    13
2.1 Asynchronous Pipelined Circuit with Blocking and Starvation    13
2.2 Buffering with Asynchronous Pipelined Circuits    15
3 Overview of Elastic Buffer    17
3.1 Elastic Buffer for Synchronous Design    17
3.2 Elastic Buffer for Asynchronous Design    18
4 Brief Architectures of Elastic Buffer    19
4.1 Proposed Architectures    19
4.2 Interfaces and Brief Architecture of Elastic Buffer    22
4.3 Butterfly State Machine    24
Chapter 3 Elastic Buffer for Four-phase and Phase-Converter    27
1 Behavior Description of Elastic Buffer    27
1.1 Store and Data Pass-Through Modes    28
1.2 Fetch and Elastic Buffer Response Modes    30
2 Storage Element and Push-channel Four-phase Elastic Buffer    31
2.1 Storage Cell for Four-phase Protocol    32
2.1.1    Data Latches and Asymmetric C-element    33
2.1.2    Store mode for Four-phase Handshaking Protocol    34
2.1.3    Fetch mode for Four-phase Handshaking Protocol    35
2.1.4    Full/Empty Detector for Four-phase Handshaking Protocol    36
2.2 Input and Output Selectors for Four-phase Protocol    38
2.2.1    Four-phase Protocol and Operation of Selector    39
2.2.2    Asynchronous Token Ring for Four-phase Protocol    40
2.2.3    Data Select Signal Generator (DG) for Four-phase Protocol    43
2.3 Handshaking Controller for Four-phase Protocol    44
2.4 Detail Architecture of Storage Element    45
2.5 Simulation Waveform of Storage Element    47
3 Two-phase Elastic Buffer for Phase-Converter    47
3.1 Send and Receive Phase-Converter    48
3.2 Simulation Waveform of phase-Converter Two-phase Elastic Buffer    49
Chapter 4 Elastic Buffer with Two-phase and Mixed-phase    51
1 True Two-phase Elastic Buffer    51
1.1 A Couple of Storage Cells for Two-phase Protocol    52
1.1.1    Store mode for Two-phase Handshaking Protocol    53
1.1.2    Fetch mode for Two-phase Handshaking Protocol    54
1.1.3    Full/Empty Detector for Two-phase Handshaking Protocol    56
1.2 Input and Output Selectors for Two-phase Protocol    57
1.2.1    Asynchronous Token Ring for Two-phase Protocol    57
1.2.2    Data Select Signal Generator (DG) for Two-phase Protocol    58
1.3 Handshaking Controller for Two-phase Protocol    59
1.4 Detail Architecture of True Two-phase Elastic Buffer    62
1.5 Simulation Waveform of True Two-phase Elastic Buffer    63
2 Mixed-phase Elastic Buffer    64
2.1 Two-to-Four mixed-phase Elastic Buffer    64
2.2 Four-to-Two mixed-phase Elastic Buffer    67
Chapter 5 Performances Analysis    70
1 Timing Constrains    70
1.1 Store Operation    70
1.2 Selector Operation    72
1.3 Phase-Converter Operation    73
2 Results and Comparisons of the Proposed Elastic Buffer    73
2.1 Timing Operation    74
2.2 Energy Consumption    77
2.3 Area    79
3 Asynchronous Pipeline Circuit with Elastic Buffer    82
3.1 Two-Stage Self Run Circuit    82
3.2 SRC Throughput    84
3.3 Simulation Results and Analysis of SRC Throughput    89
Chapter 6 Conclusions and Future Works    92
References    94

                                

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