近來高效能低耗能的的VLIW DSP處理器近來被逐漸的使用在嵌入式系統來處理影音多媒題應用程式。同時，結合MPU跟DSP雙核心處理器也被廣泛的使用在嵌入式系統中。然而可能有的應用程式太多變且複雜了，使得在這樣雙核心的系統下如何提供一個資源管理和核心溝通管理，成為一個重要的課題。

在資源管理上我們需要一個作業系統來栛助我們工作，然而不像MPU可以使用一些常見的作業系統，DSP因為架構特殊，所以設計一客製化的微核心是比較好的。此外，在雙核心的系統下，我們還需要提供友善且高效能的構通機制來栛助程式設計師來開發程式。

在本篇論文中，我們著重在PAC VLIW DSP的微核心的設計。我們說明了pCore，也就是PAC VLIW DSP上的微核心的排程設計、行程切換、行程構通、同步等等。此外我們還設計出幾個雙核心的溝通模型。並用這些模型來設計出雙核心的應用程式。最後我們在實驗中展示了pCore的各項效能，還有我們雙核心的應用程式的效能比較。

High-performance and low-power VLIW DSP processors are increasingly deployed in embedded mobile devices to process video and multimedia applications. Also, dual-core embedded processors which combine a MPU and a DSP are widely used in embedded systems to provide powerful computation. As there are diversified applications concurrently used for such systems, resource and communication management for dual-core embedded system become a focus of recent research efforts.

To manage resource, we need operating systems for both processors. And there are many popular operating systems for MPU. However, because of special architecture, DSP needs specific operating system to help it manage resource. Besides, the dualcore embedded system needs friendly and efficient communication mechanize to help programmers develop dual-core applications easily.

In this thesis, we address the microkernel design issue for a VLIW DSP processor, known as PAC architectures. We describe the detailed design of scheduler, context switch, inter-process communication, and synchronization of our microkernel system. This is known as pCore. In addition, we propose several dual-core communication model for PAC DSP and ARM based on pCore and Linux. These mechanizes can help programmers develop dual-core applications. Also, we show several dual-core JPEG encoders based on the dual-core communication models. Our experiments give the performance of pCore. It also shows the performance speedup of dual-core JPEG encoder. This is the first known implementation for dual-core systems native developed in Taiwan.

[1] Tay-Jyi Lin, Chen-Chia Lee, Chih-Wei Liu, and Chein-Wei Jen, “A Novel Register Organization for VLIW Digital Signal Processors.” Proceedings of 2005 IEEE International Symposium on VLSI Design, Automation, and Test, pages 335–338, 2005.
[2] S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, “Register organization for media processing.” International Symposium on High Performance Computer Architecture (HPCA), pp.375-386, 2000
[3] David Chih-Wei Chang, Chien-Wei Jen, I-Tao Liao, Jenq-Kuen Lee, Wen-Feng Chen, Shau-Yin Tseng, “PAC DSP Core and Application Processors..” IEEE International Conference on Multimedia & Expo (ICME), Toronto, July 9-12, 2006.
[4] Radhika, Thekkath, Susan J., “Eggers: The Effectiveness of Multiple Hardware Contexts.” ACM SIGPLAN Notices, volume 29, page(s) 328-337.
[5] A. Agarwal, B.-H. Lim, J. Kubiatowic, “EAPRIL: a Processor Architecture for multiprocessing.” Proceedings of 17th Annual International Symposium on Computer Architecture, 1998.
[6] J. Snyder, D. Whalley, T. Baker, “Fast Context Switches: Compiler and Architectural Support for Preemptive Scheduling.” Journal of Microprocessors and Microsystems (to appear).
[7] Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, S. C. Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, and Jenq Kuen Lee, “ Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors.” Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pp. 215-222, Sydney, August 16-18, 2006
[8] Ching-Ren Lee, Jenq-Kuen Lee, Ting-Ting Hwang, Shih-Chun Tsai, “Compiler optimizations on VLIW instruction scheduling for low power.” ACM Transactions on Design Automation of Electronic Systems, 8(2): 252-268 (2003).
[9] Yi-Ping You, Ching-Ren Lee, Jenq-Kuen Lee, “Compilers for Leakage Power Reductions.” ACM Transactions on Design Automation of Electronic Systems, Volume 11, Issue 1, pp. 147-166, Jan. 2006.
[10] Peng-Sheng Chen, Yuan-Shin Hwang, Dz-Ching Ju, Jenq Kuen Lee, “Interprocedural Probabilistic Pointer Analysis.” IEEE Transactions on Parallel and Distributed Systems, Volume 15, Issue 10, pp. 893-907, Oct. 2004.
[11] Cheng-Wei Chen, Yung-Chia Lin, Chung-Ling Tang, Jenq-Kuen Lee, “ORC2DSP: Compiler Infrastructure Supports for VLIW DSP Processors.” IEEE VLSI TSA, April 27-29, 2005.
[12] Anoop Gupta, Andrew Tucker and Shigeru Urushibara, “ The impact of operating system scheduling policies and synchronization methods of performance of parallel applications.” Proceedings of the 1991 ACM SIGMICS conference on Measurement and modeling of computer system.
[13] Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee, “ Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch .” Journal of VLSI Signal Processing Systems, Special Issue for PAC DSP Processor and Toolkits, Springer.
[14] ARM corporation, http://www.arm.com
[15] Linux, http://www.kernel.org
[16] ARM Linux, http://www.arm.linux.org.uk
[17] Cheng-Wei Chen, Chung-Ling Tang, Yung-Chia Lin, Jenq-Kuen Lee, “ORC2DSP: Compiler Infrastructure Supports for VLIW DSP Processors .” Proceedings of 2005 IEEE International Symposium on VLSI Design, Automation, and Test, April 27-29, 2005.
[18] Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen and Jenq Kuen Lee, “ Compiler Supports and Optimizations for PAC VLIW DSP Processors.” LCPC 2005, USA, Oct. 2005.
[19] Roy Ju, Sun Chan, and Chengyong Wu, “ Open Research Compiler for the Itanium Family.” Tutorial at the 34th Annual Int’l Symposium on Microarchitecture, Dec. 2001
[20] Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, and Klaus Erik Schauser, “Active messages: a mech-anism for integrated communication and computation.” In Proceedings of International Symposium on Computer Architecture, pages 256-166, 1992.