近幾年來，由於行動通訊技術快速發展，使得傳輸速率不斷的往上提升，例如3GPP規格中W-CDMA的最高傳輸速率也已經到達2 M bps。為了確保資料在高速傳輸下還能有較佳的傳輸品質，通道編解碼技術的良好與否，則扮演關鍵的角色，所以如何同時擁有低錯誤率與高解碼速度就成為目前主要的問題。而渦輪碼因其優異的解碼能力--幾乎逼近仙儂極限，因此廣泛被大眾所接受，然而為獲得高解碼速度，渦輪解碼器的硬體設計上也面臨到挑戰，就是複雜度、解碼性能和解碼速度彼此間的關係，必需仔細的去作取捨，找出最佳的平衡點。
本文即是針對W-CDMA規格中的渦輪解碼器硬體設計來作討論。首先我們探討編解碼過程中所需的交錯器，並且設計其硬體架構；再來是解碼器的硬體設計與實現，本文所採取的解碼理論是以SOVA演算法為主，然後在硬體上則是以複雜度最低的Two-Step SOVA架構來實現，文中討論了整個硬體的設計流程以及每個模組的詳細架構，而為了彌補SOVA先天上的缺陷，本文提出了固定通道係數與改變ACSU(Add & Compare and Select Unit)中的max模組來降低錯誤率，並且還在解碼器中加上遞迴終止模組來提升整體的解碼速度。而與解碼器相關的一些參數，例如遞迴次數、資料量化的位元數…等等，則透過軟體模擬來得到最佳的數值，以供硬體電路設計時使用。為了驗證所設計之解碼器電路效能，我們同時設計一個驗證平台，透過PCI介面，當作電腦端與解碼器電路溝通的管道，由電腦模擬產生傳送端的資料，加上通道雜訊後，經由PCI傳給FPGA上的解碼電路進行解碼的動作，然後將解碼完的資料傳回電腦端進行比對的工作，並描繪出最後訊雜比與錯誤率之間的關係，而經FPGA電路驗證後，本文所設計的SOVA解碼器電路確能在約40 M Hz的操作頻率下，達到3 M bps以上的解碼速度。

In recent years, as the result of rapid growing of the technology in mobile communication, the data transmission rate is promoting unceasingly. For example, the maximum data rate of W-CDMA in 3GPP spec is already up to 2 Mbps. To ensure the better quality of transmission at high speed, the channel encoding/decoding becomes a key issue. The main problem is how to get the low bit error rate and high decoding rate at the same time. For the former issue, the outstanding decoding ability of turbo code-- nearly approaching the Shannon limit-- has made it the widely accepted choice for use in mobile communication. But for the latter issue, there are still challenges in hardware design for turbo decoding. Tradeoffs must be made carefully between the decoding algorithm, hardware complexity, performance and decoding speed.
In this thesis, the focus is on the design and implementation of a turbo decoder complying with the W-CDMA spec. Firstly, the W-CDMA interleaver needed in the encoding/decoding process is discussed and a hardware architecture for its implementation is proposed. Then the design of the turbo decoder is considered. SOVA is the primary decoding algorithm adopted in the thesis. In particular, the Two-Step SOVA architecture is adopted because of its low complexity. Moreover, the entire design flow of the hardware architecture and the details of each module of the SOVA decoder will be discussed. In order to compensate the congenital flaw of SOVA, we proposed some approaches to lower the BER by fixing the scaling factor of the channel and by using max* in the ACSU (Add & Compare and Select Unit) instead of max module in our design. We also added an iteration termination module in the decoder to increase the whole decoding speed. The “optimal” values of pertinent parameters of the decoder, such as the iteration times, quantization levels, the scaling factor of the channel,.., etc. are first obtained by software simulation and then used in the subsequent hardware design. Finally, a PCI-based FPGA platform is utilized to verify the circuit performance of our design. Via PCI interface, a PC can transmit the channel noise corrupted data source to the SOVA turbo decoder implemented on the FPGA and receive its decoded results, and plots the BER vs. SNR. The experimental results show that the decoding rate of our design can achieve above 3 Mbps when the FPGA is operating at approximately 40 MHz.

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