研究生: |
林孝倫 Lin, Hsiao-Len |
---|---|
論文名稱: |
金屬閘極與高介電係數阻擋層對電荷陷阱式快閃記憶體元件的影響 Effects of Metal Gate and High-k Blocking Layer on Charge-Trapping Flash Memory Devices |
指導教授: |
張廖貴術
Chang-Liao, Kuei-Shu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 中文 |
論文頁數: | 86 |
中文關鍵詞: | 快閃記憶體 |
相關次數: | 點閱:2 下載:0 |
分享至: |
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就SONOS結構來說,其與浮動閘極結構元件最大的不同在於浮動閘極結構元件的穿遂氧化層厚度大約是80 □左右,而SONOS元件的穿遂氧化層厚度則大約是30□,就這樣的厚度而言,對於元件在可靠度方面的品質來說就會是一個問題,亦即,要如何在不改變穿遂氧化層厚度的前提之下,仍然能夠讓元件具有十年以上的電荷留存能力?並且在不犧牲資料留存能力的要求下在電性方面能有所提升,這些都是目前急需克服的問題。
在本論文中的研究主要分為三大方向:
(1)主要是以高介電係數材料作為元件的阻擋氧化層,而元件的底材是以N型底材為主,利用高介電係數材料的主要原因為其具有較佳的耦合率,可以有效的將阻擋氧化層上的電場耦合至穿遂氧化層,經由這樣的結構探討元件在電性及可靠度方面的改變。
(2)雖然利用高介電係數材料作為元件的阻擋氧化層,但是隨著介電係數的提升會降低材料本身的能隙,而能隙的降低對於可靠度方面會有不良的影響,因此藉由對阻擋氧化層作電漿沈浸離子佈植(Plasma immersion ion implantation,PIII)之氮化處理探討元件在電性以及可靠度方面的影響。
(3)利用功函數不同的金屬材料作為元件的閘極,因為功函數的不同會造成元件能帶彎曲程度的不同,進而影響到元件的寫入以及抹除速度,對於元件的資料留存能力也會有所影響。因此,就不同功函數的金屬閘極對元件在電性及可靠度方面的影響則是這個部分的重點。
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