簡易檢索 / 詳目顯示

研究生: 陳珮儀
Pei-Yi Chen
論文名稱: 無電鍍銅在Ta(N)阻隔層上成核與成長之研究
A Study on Nucleation and Growth of Electroless Copper on Ta(N) barrier
指導教授: 林樹均
Su-Jien Lin
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 材料科學工程學系
Materials Science and Engineering
論文出版年: 2001
畢業學年度: 89
語文別: 中文
中文關鍵詞: 無電鍍銅阻隔層濕式活化法金屬化
外文關鍵詞: electroless copper, barrier, wet activation, metallization
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本實驗以AFM、SEM、TEM研究Ta(N)/SiO2/Si無電鍍銅的成長過程,無電鍍銅前處理採用敏化活化與置換活化兩種溼式活化法。結果顯示Ta(N) 阻隔層厚度約為100 nm,表面粗糙度為0.12 nm。Ta(N)經35 °C蝕刻、60 °C敏化活化處理後,可得細小、緻密且均勻的Pd催化顆粒,大小約20-30 nm,部分Pd顆粒聚集成團,表面粗糙度為2 nm。而經室溫蝕刻、置換活化3分處理後,其Pd催化顆粒大小可達100 nm以上,表面粗糙度為15 nm;Pd顆粒的分佈明顯較敏化活化處理來得粗大而稀疏。兩種溼式活化法之Pd顆粒成長方式都是由約5 nm 的Pd晶粒堆疊聚集而成;顯然既存之Pd可以成為優先成長位置,如同自我催化一般,尤其在置換活化處理中更明顯。
    Ta(N) 敏化活化再無電鍍成長的銅膜是以3-5 nm的銅奈米晶先在Pd上堆疊成銅顆粒,再透過自我催化於銅上繼續堆疊銅奈米晶,銅顆粒彼此也可能聚集成更大的聚團;鍍覆15秒後逐漸形成有銅顆粒界線的連續銅膜,而使片電阻急遽下降,表面粗糙度也下降;鍍覆120秒則已經成為完全連續銅膜。而Ta(N) 置換活化再無電鍍成長的銅膜,因為Pd催化顆粒過於稀疏,而使銅膜成長緩慢,銅顆粒粗大;即使鍍覆5分,仍在成膜初期階段。


    摘要.......................................................I 誌謝......................................................II 總目錄....................................................Ⅳ 圖目錄....................................................Ⅶ 表目錄...................................................XⅡ 壹、前言...................................................1 貳、文獻回顧...............................................3 2-1 積體電路金屬內連線................................3 2-1-1 積體電路金屬內連線之演進..........................3 2-1-2 積體電路銅金屬內連線之沉積技術....................6 2-1-3 積體電路銅金屬內連線之製程........................6 2-2 擴散阻隔層.............................................7 2-3 無電鍍製程之前處理....................................12 2-3-1 置換活化法.......................................12 2-3-2 敏化活化法.......................................14 2-4 無電鍍銅..............................................15 2-4-1 無電鍍銅製程發展簡介.............................15 2-4-2 無電鍍銅鍍浴之組成與特性.........................16 2-4-3 無電鍍銅之化學反應式與反應機制...................19 2-4-3-1 化學反應式........................................19 2-4-3-2 反應機制[50]......................................20 2-4-4 近年來無電鍍銅在積體電路製程應用上之發展.........21 2-5 研究目的..............................................22 參、實驗步驟..............................................24 3-1 基材.............................................24 3-2 基材之前處理.....................................24 3-2-1 敏化活化處理.....................................24 3-2-2 置換活化處理.....................................26 3-3 無電鍍處理.......................................26 3-4 TEM試片製備......................................27 3-4-1 平面視野(plane-view)試片製備.....................27 3-4-2 橫截面(cross-section)試片製備....................27 3-5 微結構觀察及性質分析.............................30 3-5-1 掃描式電子顯微鏡(SEM)分析........................30 3-5-2 片電阻(sheet resistance)量測.....................30 3-5-3 原子力顯微鏡(AFM)分析............................31 3-5-4 X光繞射分析......................................31 3-5-5 穿透式電子顯微鏡(TEM)分析........................31 肆、結果與討論............................................33 4-1 擴散阻隔層.......................................33 4-2 敏化活化處理.....................................38 4-3 置換活化處理.....................................51 4-4 無電鍍銅膜.......................................58 4-4-1 微結構觀察.......................................58 4-4-2 表面粗糙度.......................................64 4-4-3 片電阻量測.......................................71 4-4-4 X光繞射分析......................................73 4-4-5 退火處理.........................................75 4-4-6 置換活化法之無電鍍銅.............................75 伍、結論..................................................81 陸、參考文獻..............................................82

    1.R. A. Levy, M. L. Green, and P. K. Gallager, “Characterization of LPCVD Aluminum for VLSI Process,” J. Electrochem. Soc., 1984, p. 2175.
    2.蔡明蒔, “半導體製程中銅電鍍技術之製程及設備,” 電子月刊, 4月號, 1999, pp. 155-161.
    3.P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, “Damascene Copper Electro-plating for Chip Interconnections,” IBM Journal of Research & Development, Vol. 42, 1998, pp. 567-574.
    4.F. B. Kaufman and D. B. Thompson, “Chemical-Mechanical Polishing for Fabricating Patterned W Metal Feature as Chip Interconnects,” J. Electrochem. Soc., Vol.138, 1991, pp. 3460-3467.
    5.B. Zaho, 1998 Symposium on VLSI Technology, Hawaii, June , 1998, pp. 28-29.
    6.D. Denning, G. Breacklmann, J.Zhang, B.Fiordalice, and Venkatramen, 1998 Symposium on VLSI Technology, Hawaii, June, 1998, pp. 22-23.
    7.Y. Morand, “Copper Metallization for Advanced IC:Requirements and Technological Solutions,” Microelectronic Engineering, Vol. 50, 2000, pp. 391-401.
    8.Y. M. Lin and S. C. Yen, “Effects of Additives and Chelating Agents on Electroless Copper Plating,” Applied Surface Science, Vol. 178, 2001, pp. 116-126.
    9.H. D. Yosi and S. Lopatin, “Integrated Electroless Metallization for ULSI,” Electrochimica Acta, Vol. 44, 1999, pp. 3639-3949.
    10.M. T. Bohr, Proceeding of the 1995 IEEE International Electron Devices Meeting, 1995, pp. 241-242.
    11.C. Whitman, M. M. Moslehi, A. Paranjpe, L. Velo, and T. Omstead, “Ultra Large Scale Integrated Metallization and Interconnects,” J. Vac. Sci. Technol. A, Vol. 17, No. 4, 1999, pp. 1893- 1897.
    12.莊達人, “VLSI製程技術,” 高立圖書公司, 6月, 1997.
    13.R. J. Contolini, L. Tarte, R. T. Graff, and L. B. Evans, “Copper Electroplating Process for Sub-Half-Micro ULSI Structure,” VMIC Conference, 1995, pp. 27-31.
    14.陳來助, “ULSI 超大型積體電路之銅導線技術,” 電子與材料, 第一期, pp. 85-92.
    15.B. Chin and P. Ding, “Barrier and Seed Layer for Damascene Copper Metallization,” Solid State Technology, Vol. 41, Issue 7, 1998, pp. 141-147.
    16.C. H. Cho, S. S. Park, and Y. Ahn, “Three-Dimensional Wafer Scale Hydrodynamic Modeling for Chemical Mechanical Polishing,” Thin Solid Films, Vol. 389, 2001, pp. 254-260.
    17.C. L. Borst, V. Korthuis, G. B. Shinn, J. D. Luttmer, R. J. Gutmann, and W. N. Gill, “Chemical-Mechanical Polishing of SiOC Organo -silicate Glasses: the Effect of Film Carbon Content,” Thin Solid Films, Vol. 385, 2001, pp. 281-292.
    18.P. Motte, J. Torres, J. Palleau, F. Tardif, O. Demolliens, and H. Bernard, “Dielectric Deposition Process for Cu/SiO2 Integration in a Dual Damascene Interconnection Architecture,” Microelectronic Engineering, Vol. 50, 2000, pp. 487-493.
    19.S. S. Wong, C. Ryu, H. Lee, and K. W. Kwon, “Barriers for Copper Interconnections,” Material Research Society Symposium Proceedings, Vol. 514, 1998, pp. 75-81.
    20.M. Stavrev, D. Fischer, F. Praessler, C. Wenzel, and K. Drescher, “Behavior of Thin Ta-Based Films in the Cu/Barrier/Si System,” J. Vac. Sci. Technol. A, Vol. 17, No. 3, 1999, pp. 993-1001
    21.T. Oku and E. Kawakami, “Diffusion Barrier Property of TaN Between Si and Cu,” Applied Surface Science, Vol. 99, 1996, pp. 365-272.
    22.謝朝全, “置換活化法在Ta(N)/SiO2/Si基材上無電鍍銅膜之研究,” 國立清華大學碩士論文, 2000年.
    23.K. H. Min, K. C. Chun, and K. B. Kim, “Comparative Study of Tantalum and Tantalum Nitrides (Ta2N and TaN) as a Diffusion Barrier for Cu Metallization,” J. Vac. Sci. Technol. B, Vol. 14, No.5, 1996, pp. 3263-3269.
    24.J. P. O’Kelly, K. F. Mongey, Y. Gobil, J. Torres, P. V. Kelly, and G. M. Crean, “Room Temperature Electroless Plating Copper Seed Layer Process for Damascene Interlevel Metal Structures,” Microelectronic Engineering, Vol. 50, 2000, pp. 473-479.
    25.J. Y. P. Wang, H. Zhang, I. Hashim, G. Dixit, and F. Chen, “TEM Analyses of Cu-Ta and Cu-TaN Interfaces,” Material Research Society Symposium Proceedings, Vol. 564, 1999, pp. 293-298.
    26.J. Dugasz and A. Szasz, “Factors Affecting the Adhesion of Electroless Coating,” Sur. Coating Technol., Vol. 58, 1993, pp. 57-63.
    27.W. D. Fields, R. N. Duncan, J. R. Zickgraf, and The ASM Committee, in Electroless Nickel Plating, Metal Handbook, 9th ed., Vol.5, American Society for Metals, 1982, Metals Park, pp. 219-235.
    28.F. Pearlstein, “Electroless Nickel Deposition,” Metal Finishing, Vol. 53, 1955, p. 59.
    29.C. Longo, P. T. Sumodjo, and F. Sanz, “Displacement Deposition of Sn from Fluoride Solutions on Pd Pre-Deposited (100) Si Substrate,” J. Electrochem. Soc., Vol. 144, 1997, pp. 1659-1663.
    30.V. M. Dubin, “Electroless Ni-P Deposition on Silicon with Pd Activation,” J. Electrochem. Soc., Vol. 139, 1992, pp. 1289-1294.
    31.V. M. Dubin, “Selective Electroless Ni-Cu(P) Deposition for Via Hole Filling and Conductor Pattern Cladding in VLSI Multilevel Interconnections Structures,” J. Electrochem. Soc., Vol. 139, 1992, pp. 1289-1294.
    32.O. M. R. Chyan, J. J. Chen, and H. Y. Chien, “Copper Deposition on HF Etched Silicon Surface:Morphological and Kinetic Studies,” J. Electrochem. Soc., Vol. 143, No. 1, 1996, pp.92-96.
    33.N. Feldstein and J. A. Weiner, “Surface Characterization of Sensitized and Activated Teflon,” J. Electrochem. Soc., Vol. 120, No.4, 1973, p. 745.
    34.R. Sard, “The Nucleation, Groeth, and Structure of Electroless Copper Deposits,” J. Electrochem. Soc., Vol. 117, No. 7, 1992, pp. 864-870.
    35.T. Homma, K. Takai, T. Osaka, Y. Yamazaki and T. Namikawa, “Transmission Electron Microscopy Study of Electroless NiP and Cu Films at Initial Deposition Stage,” J. Electrochem. Soc., Vol. 138, No. 5, 1991, p. 1269.
    36.T. Homma, T. Yamazaki, and T. Osaka, “An In Situ Study on Electroless-Deposition Process by Scanning Tunneling Microscopy”, J. Electrochem. Soc., Vol. 139, No. 3, 1992, p. 732.
    37.逢板哲爾, “化學反應製造金屬薄膜,” 表面處理工業雜誌, 3期, 1986, pp. 25-31.
    38.張中良, “非導體表面之金屬化,” 工業材料, 112期, 1996, pp. 86-92.
    39.神戶德藏著, 莊萬發譯著, “無電解鍍金,” 復漢出版社印行, 1989.
    40.J. Shu, B. P. A. Grandjean, and S. Kaliaguine, “Effect of Cu(OH)2 Electroless Copper Plating,” Ind. Eng. Chem. Res., Vol. 36, 1997, pp. 1632-1636.
    41.A. Hung and K. M. Chen, “Mechanism of Hypophosphite-Reduced Electroless Copper Plating,” J. Electrochem. Soc., Vol. 136, 1989, pp. 72-77.
    42.A. Hung and I. Ohno, “Electrochemical Study of Hypophosphite Reduced Electroless Copper Deposition,” J. Electrochem. Soc., Vol. 137, 1990, pp. 918-923.
    43.A. Hung, “Electroless Copper Deposition with Hypophosphite as Reducing Agent,” Plating and Surface Finishing, Vol. 75, 1988, pp. 62-67.
    44.J. E. A. Van den Meerakker, “On the Mechanism of Electroless Plating. II. One Mechanism for Different Reductants,” J. Appl. Electrochem., Vol. 11, 1981, pp. 387-393.
    45.齊藤圈, “金屬表面技術,” 17期, 1966, pp. 14-26.
    46.Y. M. Lin and S. C. Yen, “Effects of Additives and Chelating Agents on Electroless Copper Plating,” Applied Surface Science, Vol. 178, 2001, pp. 116-126.
    47.M. Oita, M. Matsuka, and C. Iwakura, “Deposition Rate and Morphology of Electroless Copper Film from Solutions Containing 2,2’-Dipyridyl,” Electrochimica Acta, Vol. 42, 1997, pp. 1435-1440.
    48.B. D. Barker, “Electroless Deposition of Metals,” Surface Technology, Vol. 12, 1981, pp. 77-81.
    49.H.T. Ng, S. F. Y. Li, L. Chan, F. C. Loh, and K. L. Tan, “Sequential Observation of Electroless Copper Deposition via Noncontact Atomic Force Microscopy,” J. Appl. Electrochem., Vol. 145, 1995, pp. 3301-3307.
    50.A. Hung, “Electroless Copper Deposition with Hypophosphite as Reducing Agent,” Plating and Surface Finishing, Vol. 75, 1988, pp. 62-68.
    51.V. M. Dubin and Y. Shacham-Diamand, “Selective and Blanket Electroless Copper Deposition for Ultra Large Scale Integration,” J. Electrochem. Soc., Vol. 144, 1997, p. 898.
    52.Y. Shacham-Diamand, “Electrochemical Deposition Process for ULSI Copper Interconnect Fabrication,” UCB Short Course, Jun. 1998.
    53.蔡國強, “疊層阻障層鈦/氮化鈦及氮化鉭應用於銅金屬化及鋁金屬化之研究,” 國立交通大學碩士論文, 1998年.
    54.鄧經緯, “濕式活化無電鍍銅技術在Ta(N)阻隔層上金屬化之研究,” 國立清華大學碩士論文, 2001年.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE