隨著製程技術的進步進入深次微米時代，被用來作為元件之間絕緣的淺溝絕緣結構 (Shallow trench isolation, STI) 其所引起的機械應力 (Mechanical stress) 隨著元件愈作愈小而變得愈來愈重要。根據文獻的報告，此機械應力會造成元件特性大到20%的改變，同時也發現此機械應力引起的元件特性的改變與製程和元件佈局 (Layout) 是相關的。到目前為止，元件佈局與淺溝絕緣結構機械應力效應之間的關連性並沒有一個完整清楚的說明。在這篇論文中，我們提出了指數應力分佈模型 (Exponential stress distribution model) 可以成功地解釋絕大部份有關淺溝絕緣結構機械應力效應與元件佈局之間的相關性。
元件密度隨著製程技術的進步而愈來愈高，元件在高溫的操作也因而愈來愈普遍；有關淺溝絕緣結構機械應力效應的溫度效應，第一次在這篇論文中被徹底的探討。對N型金氧半場效電晶體 (N-MOSFET) 而言，我們發現隨著操作溫度的升高，淺溝絕緣結構機械應力效應會被稍微地減輕。同時在這篇論文中，我們也得到了一個簡單的經驗式子，讓電路設計者可以很容易地把淺溝絕緣結構機械應力效應的溫度效應也考慮進去。
為了克服淺溝絕緣結構機械應力效應，在不改變元件製程的情況下，我們提出了一個新的元件結構，可以有效地降低淺溝絕緣結構機械應力效應。在論文中我們証實了由於淺溝絕緣結構機械應力在新的元件結構中被有效的降低，所以新的元件結構所顯現的淺溝絕緣結構機械應力效應也比在傳統結構上要來得小。
而在元件雜訊方面，對N型金氧半場效電晶體而言，我們証實了元件雜訊特性受淺溝絕緣結構機械應力的影響並不大。

Shallow trench isolation induced mechanical stress has become more and more important as the dimension of devices scaling-down continuously. The stress can induce the variation of device’s performance as large as 20% depend on processes and layout of devices. Up to now, the layout dependence of the STI mechanical stress effect has not been understood clearly. In this thesis, we have proposed an exponential stress distribution model successfully explaining most of the behaviors of the layout dependent STI-induced mechanical stress effect.
Temperature dependence of STI mechanical stress effect has been studied thoroughly for the first time in this thesis. According to the results, increased operating temperature results in a slight reduction of the drive-current degradation caused by STI-induced mechanical stress for n-MOSFET. An empirical formula was obtained and can be taken into account in IC design easily.
In order to overcome STI-induced mechanical stress effect, we have proposed a new method to improve the stress effect by changing the structure of n-MOSFET without any modification of processes. It has been proved that the new structured devices are less sensitive to STI-induced mechanical stress effect than conventionally structured devices due to the stress reduction in newly structured devices.
In the noise point of view, we have shown that noise characteristics are insensitive to STI-induced mechanical stress.

[1] R. J. Jaccodine and W. A. Schleget, "Measurement of Strains at Si-SiO2 Interface," J. Appl. Phys., vol. 37, pp. 2429-2434, 1966.
[2] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, C. Raynaud, "Electrical Analysis of Mechanical Stress Induced by Shallow Trench Isolation," Eur. Solid-State Device Conf., 33rd, pp. 359-362, 2003.
[3] Gregory Scott, Jeffrey Lutze, Mark Rubin, Faran Nouri, and Martin Manley, "NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress," in IEDM Tech. Dig., pp. 827-830, 1999.
[4] Richard C. Jaeger, Jeffrey C. Suhling, Ramanathan Ramani, Arthur T. Bradley, and Jianping Xu, "CMOS Stress Sensors on (100) Silicon," IEEE Solid-State Circuits vol. 35, no. 1, pp. 85-95, 2000.
[5] R. A. Bianchi, G. Bouche, O. Roux-dit-Buisson, "Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance," in IEDM Tech. Dig., pp. 117-120, 2002.
[6] Ke-Wei Su, Yi-Ming Sheu, Chung-Kai Lin, Sheng-Jier Yang, Wen-Jya Liang, Xuernei Xi, chung-shi Chiang, Jaw-Kang Her, Yu-Tai Chia, Carlos H. Diaz, and Chenming Hu, "A Scaleable Model for STI Mechanical Stress Effect on Layout Dependence of MOS Electrical Characteristics," IEEE Custom Integrated Circuits Conf., pp. 245-248, 2003.
[7] Y. M. Sheu, Kelvin Y. Y. doong, C. H. Lee, M. J. chen, and C. H. Diaz, "Study on STI Mechanical Stress Induced Variations on Advanced CMOSFETs," Int. Conf. on Microelectronic Test Structure, pp. 205-208, 2003.
[8] Y.G. Wang, D.B. Scott, J. Wu, J.L. Waller, J.Hu, K. Liu, and V. Ukraintsev, "Effect of Uniaxial Mechanical Stress on Drive Current of 0.13 um MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 2, pp. 529-531, 2003.
[9] Y. Jeon, G. C. -F. Yeap, P. Grudowski, T. Van Gompel, J. Schmidt, M. Hall, B. Melnick, M. Mendicino, S. Venkatesan, "The impact of STI mechanical Stress on the device performance of 90nm technology node with different substrates and isolation processes," in Proc. IEEE Int. SOI Conf., pp. 164-165, 2003.
[10] Tony Lin, Yoyi Gong, J. T. Tseng, Lorenzo Yu, Tzermin Shen, Daniel Chen, T. P. Chen, C. L. Kuo, W. T. Shiau, J. K. Chen, S. C. Chien, and S. W. Sun, "Optimization of STI Stress and Active Geometry Configuration for Advanced CMOS Devices," J. Appl. Phys., vol. 43, no. 4B, pp.1756-1758, 2004.
[11] Masafumi Miyamoto, Hiroyuki Ohta, Yukihiro Kumagai, Yasuo Sonobe, Kousuke Ishibashi, and Yasushi Tainaka, "Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics," IEEE Trans. Electron Devices, vol. ED-51, no.3, pp. 440-443, 2004.
[12] Heemyong Park, Kevin S. Jones, Jim A. Slinkman, and Mark E. Law, "The Effects of Strain on Dopant Diffusion in Silicon," in IEDM Tech. Dig., pp. 303-306, 1993.
[13] Shinya Ito, Hiroaki Namba, Kensuke Yamguchi, Tsuyoshi ahairata, Koichi Ando, Shin Koyama, Shunichiro Kuroki, Nobuyuki Ikezawa, Tatsuya Suzuki, Takehiro Saitoh, and Tadahiko Horiuchi, "Mechanicl Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design," in IEDM Tech. Dig., pp. 247-250, 2000.
[14] Willem-Jan Toren, Emmanuel Perrin, Meindert Lunenborg, "Characterization of the diode leakage current in advanced 0.12μm CMOS technology," Extended Abstracts of int. Workshop on Junction Tech., pp. 15-18, 2001.
[15] Hyeokjae Lee, Jong-Ho Lee, Hungsoon Shin, Young-June Park, and Hong Shick Min, "An Anomalus Device Degradation of SOI Narrow Width Devices Caused by STI Edge Influence," IEEE Trans. Electron Devices, vol. ED-49, no. 4., pp. 605-612, 2002.
[16] Scott R. Stiffler, Jerry B. Lasky, Charles W. Koburger, and Wayne S. Berry, "Oxidation-Induced Defect Generation in Advanced DRAM Structures," IEEE Trans. Electron Devices, vol. ED-37, no.5, pp. 1253-1258, 1990.
[17] Chih-Hsin Yu, Min-hwa Chi, Yuan-Hung Liou, Yeur-Luen Tu, Chi-San Wu, Yu-Shen Chen, Chih-Yang Pai, and Chia-Shiung Tsai, "Plasma charging Defect Characterization, Inspection, and Monitors in Poly-Buffered STI," IEEE Trans. Semiconductor Manufacturing, vol. 15, no. 4, pp. 478-485, 2002.
[18] T. Kuroi, T. Uchida, K. Horita, Horita, M. Sakai, Y. Inoue, and T. Nishimura, "Stress Analysis of Shallow Trench Isolation for 25MDRAM and beyond," in IEDM Tech. Dig., pp. 141-144, 1998.
[19] Peter Smerys, Peter B. Griffin, Zofia U. Rek, Ingrid De Wolf, and Krisna C. Saraswat, "Influence of Process-Induced Stress on Device Characteristics and its Impact on Scaled Device Performance," IEEE Trans. Electron Devices, vol. ED-46, no.6, pp. 1245-1252, 1999.
[20] Astuki Ono, Ryuichi Ueno, and Issmi Sakai, "TED Control Technology for Suppression of Reverse Narrow Channel Effect in 0.1 um MOS Devices," in IEDM Tech. Dig., pp. 227-230, 1997.
[21] J. Damiano, C. K. Subramanian, M. Gibson, Y. -S. Feng, L. Zeng, J. Sebek, E. Deeters, C. Feng, T. Mcnelly, M. Blackwell, H. Nguyen, H. Tian, J. Scott, J. Zaman, C. Honcik, M. Miscione, K. Cox, J. D. Hayden, "Characterization and Elimination of Trench Dislocations," VLSI Symp. Tech. Dig., pp212-213, 1998.
[22] H. Miura, S. Ikeda, and N. Suzuki, "Effect of mechanical Stress on Reliability of Gate-Oxide Film in MOS Transistors," in IEDM Tech. Dig., pp. 743-746, 1996.
[23] Shuji Ikeda, Hiroyuki Ohta, Hideo Miura, and Yasuhide Hagiwara, "Mechanical Stress Control in a VLSI-Fabrication Process: A Method for Obtaining the Relation Between Stress Levels and Stress-Induced Failures," IEEE Trans. Semiconductor Manufacturing, vol. 16, no. 4, pp. 696-703, 2003.
[24] William G. En, Dong-Hyuk Ju. Darin Chan, Simon Chan, and Olov Karlsson, "Reduction of STI/active Stress on 0.18μm SOI Devices Through Modification of STI Process," in Proc. IEEE Int. SOI Conf., pp. 85-86, 2001.
[25] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, "Local Mechancial-Stress Control(LMC): A New Technique for CMOS-Performance Enhancement," in IEDM Tech. Dig., pp. 433-436, 2001.
[26] Fabiano Fruett, Gerard C. M. Meijer, and Anton Bakker, "Minimization of the Mechanical-Stress-Induced Inacuracy in Bandgap Voltage References," IEEE Solid-State Circuits. vol. 38, no. 7, pp. 1288-1291, 2003.
[27] Stanley Wolf, Silicon Processing for the VLSI ERA , vol. 4, part 1, Lattice Press.
[28] S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1993.
[29] Cheng-Liang Huang, Hamid Soleimani, Greg Grula, Narain D. Arora, and Dimitri Antoniadis, "Isolation Process Dependence of Channel Mobility in Thin-Film SOI Devices," IEEE Electron Device Lett., vol. 17, no. 6, pp. 291-293, 1996.
[30] Jian Chen, Moses Chan, Ingrid De Wolf, "Local Stress Measurements in Package by Raman Spectroscopy," Electronics Packaging Tech. Conf., pp. 159-162, 2000.
[31] Daewon Ha, Changhyun Cho, Dongwon Shin, Gwan-Hyeob Koh, Tae-Young Chung, and Kinam Kim, "Anomalous Junction Leakage Current Induced by STI Dislocation and Its Impact on Dynamic Random Access Memory Devices," IEEE Trans. Electron Devices, vol. ED-46, no.5, pp. 940-146, 1999.
[32] Venkatesh P. Gopinath, Helmut Puchner, and Mohammad Mirabedini, "STI Stress-Induced Increase in Reverse Bias Junction Capacitance," IEEE Electron Device Lett., vol. 23, no. 6, pp. 312-314, 2002.
[33] Peter Smeys, Peter B. Griffin, Zofia U. Rek, Ingrid De Wolf, and Krishan C. Saraswat, "The influence of oxidation-induced stress on the generation current and its impact on scaled device performance," in IEDM Tech. Dig., pp. 709-712, 1996.
[34] Ke-Wei Su, Kuang-Hsin Chen, Tang-Xuan Chung, Hung-Wei Chen, Cheng-Chuan Huang, Hou-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Cheng-Kuo Wen, Yi-Ming Sheu, Sheng-Jier Yang, Chung-Shi Chiang, Chien-Chao Huang, Fu-Liang Yang, and Yu-Tai Chia, "Modeling Isolation-Induced Mechanical Stress Effect on SOI MOS Devices," in Proc. IEEE Int. SOI Conf., pp. 80-82, 2003.
[35] V. Senez, T. Hoffmann, E. Robilliart, G. Bouche, H. Jaouen, M. Lunenborg, and G. Carnevale, "Investigations of Stress Sensitivity of 0.12 CMOS Technology Using Process Modeling," in IEDM Tech. Dig., pp. 831-834, 2001.
[36] Kazunari Ishimaru, Jone F. Chen, and Chenming Hu, "Channel Width Dependence of Hot-Carrier Induced Degradation in Shallow Trench Isolated PMOSFET's," IEEE Trans. Electron Devices, vol. ED-46, no.7, pp. 1532-1536, 1999.
[37] Bernd Borchert, and Gerhard E.Eorda, "Hot-Electron Effects on Short-Channel MOSFET's Determined by the Piezoresistance Effect," IEEE Trans. Electron Devices, vol. ED-35, no.4, pp. 483-488, 1988.
[38] Z. Z. Wang, J. Suski, and D. Collard, "Piezoresistive Simulation in MOSFETs," Sensors and Actuators A, 37-38, pp. 357-364, 1993.
[39] Scott E. Thompson, Mark Armstong, Chis Auth, Steve Cea, Robert Chau, Glenn Glass, Thomas Hoffman, Jason Klaus, Zhiyong Ma, Brian Mcintyre, Anand Murthy, Borna Obradovic, Lucian Shifren, Sam Sivakumar, Sunit Tyagi, Tahir Ghani, Kaizad Mistry, and Youssef EI-Mansy, "A Logic Nanotechnology Featuring Strained-Silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, 2004.
[40] Akemi Hamada, Takeharu Furusawa, Naota Saito, and Eiji Takeda, "A New Aspect of Mechanical Stress Effects in Scaled MOS Devices," IEEE Trans. Electron Devices, vol. ED-38, no.4, pp. 895-900, 1991.
[41] Tung-Sheng Chen, and Yu-Ren Huang, "Evaluation of MOS Devices as Mechanical Stress Sensors," IEEE Trans. Comp. and Packag. Technol. vol. 25, no. 3, pp. 511-517, 2002.
[42] Cheng-Liang Huang, Hamid R. Soleimani, Gregory J. Grula, Jeffrey W. Sleight, Angelo Villani, Hassan Ali, and Dimitri A. Antoniadis, "LOCOS-Induced Stress Effects on Thin-Film SOI Devices," IEEE Trans. Electron Devices, vol. ED-44, no.4, pp. 646-650, 1997.
[43] Arthur T. Bradley, Richard C. Jaeger, Jeffrey C. Suhling, and Kevin J. O'Conor, "Piezoresistive characteristics of Short-channel MOSFETs on (100)silicon," IEEE Trans. Electron Devices, vol. ED-48, no. 9, pp. 2009-2015, 2001.
[44] Robin Degraeve, Guido Groeseneken, Ingrid De Wolf, and Herman E. Maes, "The Effect of Externally Imposed Mechanical Stress on the Hot-Carrier-Induced Degradation of Deep-Sub Micron nMOSFET's," IEEE Trans. Electron Devices, vol. ED-44, no.6, pp. 943-950, 1997.
[45] Hissayo Sasaki Momose, Toyota Morimoto, Kikuo Yamabe, and Hiroshi Iwai, "Relationship Between Mobility and Residual-Mechanical-Stress as Measured by Raman Spectroscopy for Nitrided-Oxide-Gate MOSFETs," in IEDM Tech. Dig., pp. 65-68, 1990.
[46] B-Y. Tsaur, John C. C. Fan, and M. W. Geis, "Stress-Enhanced Carrier Mobility in Zone Melting Recrystallized Polycrystalline Si Films on SiO2-Coated Substrates," Appl. Phys. Lett., vol. 40, no. 4, pp. 322-324, 1982.
[47] Hyeokjae Lee, Jong-Ho Lee, Hyungsoon Shin, Young June Park, and Hong Shick Min, "Low-Frequency Noise Degradation Caused by STI Interface Effects in SOI-MOSFETs," IEEE Electron Device Lett., vol. 22, no.9, pp. 449-451, 2001.
[48] Sandip Tiwari, M. V. Fischetti, P. M. Mooney, and J. J. Welser, "Hole Mobility Improvement in Silicon-on-Insulator and Bulk Silicon Transistors Using Local Strain," in IEDM Tech. Dig., pp. 939-941, 1997.
[49] Chih Yuan Lu, and J. M. Sung, "Reverse Short-Channel Effect on Threshold Voltage in Submicrometer Salicide Devices," IEEE Electron Device Lett., vol. 10, no.10, pp. 446-448, 1989.
[50] Jong-Wook Lee, Hyung-Ki Kim, Min-Rok Oh, and Yo-Hwan Koh, "Threshold Voltage Dependence of LOCOS-Isolated Thin-Film SOINMOSFET on Buried Oxide Thickness," IEEE Electron Device Lett., vol. 20, no.9, pp. 478-480, 1999.
[51] S. W. Crowder, P. M. Rousseau, J. A. Scott, P. B. Griffin, and J. D, Plummer, "The Effect of Source/Drain Processing on the Reverse Short Channel Effect of Deep Sub-Micron Bulk and SOINMOSFETs," in IEDM Tech. Dig., pp. 427-430, 1995.
[52] Hyeokjae Lee, Kwun-Soo Chun, Jeong-Hyong Yi, Jong Ho Lee, Young June Park, and Hong Shick Min, "Harmonic Distortion due to Narrow Width Effects in Deep sub-micron SOI-CMOS Device for analog-RF applications," in Proc. IEEE Int. SOI Conf., pp. 83-85, 2002.
[53] Miroslav Micovic, Ara Kurdoghlian, Paul Janke, Paul Hashimoto, Danny W. S. Wong, Jeong S. Moon, Loren McCray, and chanh Nguyen, "AlGaN/GaN Heterojunction Field Effect Transistors Grown by Nitrogen Plasma Assisted Molecular Beam Epitaxy," IEEE Trans. Electron Devices, vol. ED-48, no. 3, pp. 591-596, 2001.