在執行最佳化與平行化以開發先進硬體架構之特色的同時，編譯器為了提升程式執行的效能，需要量化地評估各種轉換後的效益。假如指標別名(alias)關係發生的機率很高或很低，則一些有用的最佳化與平行化的方法將可以被應用。例如，假如發生的機率很低，編譯器將可轉換程式去完成推測式資料存取、或將每個loop iteration在推測式多執行緒(speculative multithreading)架構下執行、或避免產生特殊的程式碼。因此，對於編譯器而言，整合能夠量化指標關係的指標分析方法是非常重要的。然而，傳統的機率分析技巧並沒有提供量化的資訊，本論文提出一機率化指標分析的方法來計算程式中每個指標關係發生的機率。我們所提出的方法包含了elimination algorithm與 iterative algorithm。我們同時也實作了一編譯器原型來完成跨程序的機率化指標分析，實驗結果顯示我們所提出的方法可以精確的估計指標關係的機率，對於實驗中所測試的效能評估程式，我們得到平均約4.61%的誤差。
除此之外，我們同時也將此機率化指標分析的資訊應用在推測式多執行緒架構上的編譯器最佳化之研究，推測式多執行緒(SpMT)架構可以開發無法在靜態分析上所獲得的程式平行度。在這種架構下，程式效能的增加主要來自於推測式的執行緒同時執行，然而，假如執行緒之間有高度相依性，則程式的效能反而會降低，這是由於執行緒推測錯誤將啟動回復機制，而回復機制會造成程式執行上很大的負擔，因此，在推測式多執行緒的架構下，如何量化相依性的關係，並依照此資訊，當相依性關係大於某個值時，就關閉推測式多執行緒的執行方式是非常重要的。本論文，我們亦提出了量化loop iteration間相依性關係的方法，此資訊可以用來決定是否應該使用推測式多執行緒來執行loop iteration。這部分的技術包含兩個階段，首先是利用機率化的指標分析計算指標關係的機率，接著利用此資訊進一步計算loop iteration間的相依性之機率。實驗結果顯示我們所提出的方法將正確的指導編譯器是否應該使用推測式的機制，對於推測式多執行緒架構，在效能上有顯著的改進。

When performing aggressive optimizations and parallelization to exploit features of advanced architectures, optimizing and parallelizing compilers need to quantitatively assess the profitability of any transformations in order to achieve high performance. Useful optimizations and parallelization can be performed if it is known that certain points-to relationships would hold with high or low probabilities. For instance, if the probabilities are low, a compiler could transform programs to perform data speculation or partition iterations into threads in speculative multithreading, or it would avoid conducting code specialization. Consequently, it is essential for compilers to incorporate pointer analysis techniques that can estimate the possibility for every points-to relationship that it would hold during the execution. However, conventional pointer analysis techniques do not provide such quantitative descriptions and thus hinder compilers from more aggressive optimizations, such as thread partitioning in speculative multithreading, data speculations, code specialization, etc.
This thesis addresses this issue by proposing a probabilistic points-to analysis (PPA) technique to compute the probability of every points-to relationship at each program point. Based on the foundation of data-flow analysis, an elimination algorithm and an iterative algorithm were developed respective to handle and solve the related problems of probabilistic interprocedural points-to analysis. A prototype compiler has been implemented upon the SUIF system to perform the interprocedural probabilistic points-to analysis. Experimental results show this technique can estimate the probabilities of points-to relationships in benchmark programs with reasonable small
errors, about 4.61% in average.

In additions, we present an application of adopting probabilistic points-to information into compiler optimizations for speculative multithreading architecture.
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threads in parallel that are extracted from a sequential program. However, performance degradation might happen if the threads are highly dependent, since a
recovery mechanism will be activated when a speculative thread executes incorrectly and such a recovery action usually incurs a very high penalty. Therefore, it is essential for SpMT to quantify the degree of dependences and to turn off speculation if the degree of dependences passes certain thresholds. We propose a technique that quantitatively computes dependences between loop iterations and such information can be used to determine if loop iterations can be executed in parallel by speculative threads. This technique can be broken into two steps. First probabilistic points-to analysis is performed to estimate the probabilities of points-to relationships in case there are pointer references in programs, and then the degree of dependences between loop iterations is computed quantitatively. Experimental results show compiler-directed
thread-level speculation based on the information gathered by this technique can achieve significant performance improvement on SpMT.

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