研究生: |
梁慶儀 Liang, Cing-Yi |
---|---|
論文名稱: |
應用5G混合式自動重送請求機制之硬體友善的低密度奇偶檢查解碼排程 Hardware-friendly LDPC Decoding Scheduling for 5G HARQ Applications |
指導教授: |
翁詠祿
Ueng, Yeong-Luh |
口試委員: |
王忠炫
Wang, Chung-Hsuan 李晃昌 Lee, Huang-Chang |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 中文 |
論文頁數: | 35 |
中文關鍵詞: | 低密度奇偶檢查碼 、5G 、混合式自動重送請求 、Chase合併 、增量冗餘 |
外文關鍵詞: | LDPC codes, 5G, HARQ, Chase combining, incremental redundancy |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
此篇論文提出應用混合式自動重送請求(hybrid automatic repeat request)機制之硬體友善的5G低密度奇偶檢查(low-density parity-check)解碼排程。因為在奇偶檢驗矩陣(parity-check matrix)中有內建的穿刺區塊,此特性會造成解碼時間變長,為了減少解碼所需的迭代次數,我們分別針對第一次解碼、使用Chase合併(Chase combining)的混合式自動重送請求,和使用增量冗餘(incremental redundancy)的混合式自動重送請求提出較有效率的解碼排程。我們提出的排程能夠在第一次解碼中,根據穿刺沿的數量進行排程,能夠有效率的先復原穿刺節點後,再接續後面的解碼運算。在使用Chase合併的混合式自動重送請求時,我們保留穿刺部分的前次解碼結果,並根據列權重進行排程。在使用增量冗餘的混合式自動重送請求時,我們先傳送對應到奇偶檢驗矩陣中純列正交(pure-row-orthognal)部分的奇偶位元。根據硬體實現的結果,當碼率為0.303時,在第一次解碼中的吞吐量可以增加21.37%,在Chase合併之混合式自動重送請求下可增加56.9%,而在增量冗餘之混合式自動重送請求下可增加14.51%。
This paper presents hardware-friendly LDPC decoding schedules for 5G hybrid automatic repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity check matrix (PCM), a scheduling technique is proposed that allows the punctured nodes to be efficiently recovered. For HARQ using the Chase combining (CC), the previous decoding results corresponding to the punctured part are retained, and the proposed layered decoding is arranged according to the row weight. For HARQ using the incremental redundancy (IR) approach, the parity bits corresponding to the pure-row-orthogonal part of the PCM are transmitted first. The hardware implementation shows that the throughput can be increased by 21.37% for the first decoding attempt, 56.9% for CC-HARQ and 14.51% for IR-HARQ when the code rate reaches 0.303.
[1] R. Gallager, "Low-density parity-check codes," IRE Transactions on Information Theory, pp. 21-28, 1962.
[2] D. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Transactions on Information Theory, vol. 45, no. 2, pp. 399-431, 1999.
[3] J. C. J. Chen and P. Fossorier, "Density evolution for BP-based decoding algorithms of LDPC codes and their quantized versions," IEEE Global Telecommunications Conference, vol. 2, no. 5, pp. 1378-1382, 2002.
[4] M.-R. Li, C.-H. Yang and Y.-L. Ueng, "A 5.28-Gb/s LDPC decoder with time-domain signal processing for IEEE 802.15.3c applications," IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 592-604, Feb. 2017.
[5] J. Zhang and M. Fossorier, "Shuffled belief propagation decoding," Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 8-15, 2002.
[6] C. A. Aslam, Y.-L. Guan, K. Cai, "Improving the belief-propagation convergence of irregular LDPC codes using column-weight based scheduling," IEEE Communications Letters, vol. 19, no. 8, pp. 1283-1286, AUG. 2015.
[7] H.-C. Lee and Y.-L. Ueng, "LDPC decoding scheduling for faster convergence and lower error floor," IEEE Transactions on Communications, vol. 62, no. 9, pp. 3104-3113, 2014.
[8] H.-C. Lee and Y.-L. Ueng, "Incremental decoding schedules for puncture-based rate-compatible LDPC codes," IEEE 83rd Vehicular Technology Conference (VTC Spring), pp. 1-5, 2016.
[9] H.-C. Lee, Y.-L. Ueng, S.-M. Yeh, and W.-Y. Weng, "Two informed dynamic scheduling strategies for iterative LDPC decoders," IEEE Transactions on Communications, vol. 61, no. 3, pp. 886-896, 2013.
[10] J. Ha, D. Klinc, J. Kwon, and S. W. Mclaughlin, "Layered BP decoding for rate-compatible punctured LDPC codes," IEEE Communications
Letters, vol. 11, no. 5, pp. 440-442, 2007.
[11] Y. Wu and H. Yang, :Optimising energy efficiency of LDPC coded Chase combining HARQ system," Electronics Letters, vol. 51, no. 6, pp. 490-492, 2015.
[12] H.-C. Lee, M.-R. Li, J.-K. Hu, P.-C. Chou, and Y.-L. Ueng, "Optimization techniques for the efficient implementation of high-rate layered QC-LDPC decoders," IEEE Transaction on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 457-470, 2017.
[13] H.-J. Kang, B.-D. Yang, "Low-complexity, high-speed multi-size cyclic-shifter for quasi-cyclic LDPC decoder," Electronics Letters, vol. 54, pp. 452-454, 2018.
[14] Y.-L. Ueng, Y.-L. Wang, C.-Y. Lin, J.-Y Hsu, and P. Ting, "Modiffied layered message passing decoding with dynamic scheduling and early termination for QC-LDPC codes," IEEE International Symposium on Circuits and Systems, pp. 121-124, 2009.