We propose a partitioning approach for the Chipsburger platform-based 3D IC methodology. We employ a hierarchical design framework for its low complexity, small solution space, and high performance. Our approach minimizes the manufacturing cost under different volume requirements while generating a platform for a set of applications. It further partitions the platform and remaining circuits into dies. Our cost model takes into account IP fee, TSV cost, die cost, and NRE cost. User specifications include the number and area of the platform dies and the production volume of each application. Our approach effectively reduces the total design-and-manufacturing cost of a set of applications.

我們提出一個適用於以平臺為基礎的三維積體電路的分割方法。 此方法採用階層式設計架構，用以降低設計複雜度、減小可能結果的存在空間、提高設計效能。此方法針對不同製造數量的應用，建立一個適用於各應用的平臺，以達到降低製造成本的目標。此方法將平臺及各應用餘下的部分，更進一步分割成多層晶片。我們採用的成本模型會將矽智財費用、穿層導線的成本、晶片製造的成本、一次性工程費用納入考量。此方法中，使用者可自行定義的項目包含分割後平臺的晶片數、單層平臺晶片的面積、各應用的製造數量。我們的方法有效的降低數個應用的整體設計製造成本。

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