研究生: |
吳東駿 Wu, Dong-Jyun |
---|---|
論文名稱: |
一個十二位元每秒一億次取樣的連續漸進式類比數位轉換器使用數位錯誤校正系統與回切電容架構 A 12-bit 100MS/s Successive-Approximation Analog-to-Digital Converter with Digital Error Correction and Correlated-Reversed Switching |
指導教授: |
朱大舜
Chu, Ta-Shun 彭朋瑞 Peng, Pen-Jui |
口試委員: |
王毓駒
Wang, Yu-Jiu 吳仁銘 Wu, Jen-Ming |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2023 |
畢業學年度: | 112 |
語文別: | 英文 |
論文頁數: | 79 |
中文關鍵詞: | 連續漸進式類比數位轉換器 、訊號中和技術 、冗餘技術 、相關反向切換技術 、回切電容演算法 |
外文關鍵詞: | SAR ADC, Neutralization technique, Redundancy technique, Correlated Reversed Switching technique, Bidirectional Algorithm |
相關次數: | 點閱:57 下載:4 |
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本論文提出一個十二位元每秒取樣一億次的連續漸進式類比數位轉換器,在高速操作的連續漸進式類比數位轉換器,由於每次比較的時間非常短,常常在C-DAC電壓還沒穩定的時候就必須要做下一次的比較,因此C-DAC電壓穩定的問題嚴重影響電路的效能,也限制了電路的操作速度,這邊採用二進位重組加權電容陣列與數位錯誤校正電路去避免錯誤的比較結果帶來錯誤的轉換結果,同時比較器可以在C-DAC還沒穩定的時候先做比較,以提升電路操作速度;加上回切電容架構去避免不必要的電容切換,也避免電容容值失真時帶來的非線性行為。
使用TSMC 65nm 1P9M製程,在供應電壓為1.2V,在高頻接近尼奎斯特頻率之下,輸入訊號為49.6094 MHz,訊噪失真比(SNDR)為72.2 dB,有效位元數(ENOB)為11.69 bits,平均消耗功率為2.461 mW。在低頻輸入訊號為11.3281 MHz,訊噪失真比(SNDR)為72.4 dB,有效位元數(ENOB)為11.74 bits, 平均消耗功率為2.227 mW,核心電路面積為0.1084平方公釐。
This thesis is a 12-bit 100 MS/s SAR ADC. In high-speed operation of SAR ADC, due to the very short time per comparison cycle, omparison often need to be made before the C-DAC voltage stabilizes. This issue severely affects the circuit's performance and limits its operating speed. To address this, a binary search with recombination and digital error correction circuit are adopted to avoid wrong comparison outcome result in wrong conversion output. Additionally, the comparator can perform comparison before the C-DAC voltage stabilize, thereby improving the circuit's operating speed. Furthermore, correlated-reversed switching is employed to avoid unnecessary capacitor switching and prevent non-linear effect due to capacitor mismatch.
Using TSMC 65nm 1P9M process, the supply voltage is 1.2 V. Operating at high frequency close to the Nyquist frequency, the input signal is 49.6094 MHz. The SNDR is 72.2 dB, ENOB is 11.69 bits, and the average power consumption is 2.461 mW. At low frequencies, the input signal is 11.3281 MHz. The SNDR is 72.4 dB, ENOB is 11.74 bits, and the average power consumption is 2.227 mW. The core circuit area is 0.1084 mm2.
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