簡易檢索 / 詳目顯示

研究生: 方上維
Shang-Wei Fang
論文名稱: 探討分佈性寫入抹除循環對NROM資料保存可靠度之研究與改良
The Study and Improvement of NROM Retention with Distributive Cycling Stresses
指導教授: 林崇榮
Chrong-Jung Lin
金雅琴
Ya-Chin King
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 中文
論文頁數: 78
中文關鍵詞: NROMSONOS快閃記憶體資料保存力
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 一個有發展性的快閃記憶體元件NROM已經在近幾年中被提出,其電荷是以局部性儲存於氮化矽層中。本篇論文將討論NROM在寫入抹除週期中加入分佈性延遲與閘極偏壓產生之修復效應與電荷垂直重新分佈現象對元件資料保存力的影響。這裡指的修復效應是對寫入抹除循環中在底部氧化層產生之損傷作修補的動作進而有效的改善高溫時的資料保存力,一些不同的分佈操作對應不同之修復情況和資料保存力特性也一併被討論,然後一個對應NROM分佈性寫入抹除週期的資料保存力模型也被應用來作生命期的預測。此外,一個新的兩步驟抹除之寫入抹除循環也被提出來進一步改善資料保存力,其操作方式是在抹除後加一個額外的閘極脈衝。這個新的寫入抹除週期操作可以改變NROM元件儲存之電荷的分佈情形(以電荷汲引量測技術來偵測其電荷位置),可得出一個在高溫資料保存力中收縮的臨界電壓變化。從本篇論文的研究結果,我們成功的達成了在高密度記憶體元件應用上,對資料保存力可靠度改善的目的。


    摘要 Abstract 致謝 目錄 附圖目錄 附表目錄 第一章 緒論 1.1 非揮發性記憶體介紹 1.2 研究動機 1.3 論文大綱 第二章 回顧與發展 2.1 SONOS與NROM的發展過程 2.2 改良SONOS資料保存力相關論文之回顧 2.2.1 氧化鋁替代阻擋氧化層之結構(SANOS) 2.2.2 能帶工程之SONOS結構(BE-SONOS) 2.2.3 寫入機制為熱電洞注入之氮化矽電子儲存結構(PHINES) 2.3 相關SONOS資料保存力改良方法之比較 第三章 元件製程與基本操作機制 3.1 NROM元件製程與結構 3.2 NROM基本操作機制 3.2.1 NROM的寫入機制 3.2.2 NROM的抹除機制 3.2.3 NROM的讀取機制 第四章 NROM在寫入抹除循環中的修復效應 4.1 分佈性寫入抹除循環的操作機制 4.2 分佈性寫入抹除循環對應資料保存力的修復效應 4.3 資料保存力的溫度效應 4.4 資料保存力之模型探討 4.4.1 NROM之資料保存力可靠性模型 4.4.2 氮化矽電荷反向穿隧模型 第五章 兩步驟抹除之寫入抹除循環(TSEC)操作 5.1 TSEC的操作機制 5.2 TSEC的資料保存力 5.3 TSEC操作條件的最佳化 5.4 TSEC操作後的電荷重新分佈探討 5.5 元件電性模擬之驗證 5.6電荷汲引技術對TSEC之電荷分佈的驗證 第六章 結論 附錄A 電荷汲引技術的量測方法 參考文獻

    參考文獻

    [1] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, “ A New Flash EEPROM Cell Using Triple Polysilicon Technology, ” Int. Electron Devices Meeting Tech. Dig., 1984, pp. 464-467.
    [2] S. Pan, C. C. Yeh, R. Liu, and C. Y. Lu, “ Nonvolatile Memory Challenges toward Gigabit and Nano-scale Era and a Nano-scale Flash Cell: PHINES, ” Int. Conf. on Solid State Devices and Materials, 2002, pp. 152-153.
    [3] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “ NROM: A Novel Localized Trapping, 2bit Nonvolatile Memory Cell, ” IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
    [4] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. H. Wang, S. Pan, C. Y. Lu, and S. H. Gu, “ Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell, ” Int. Electron Devices Meeting Tech. Dig., 2001, pp. 32.6.1-32.6.4.
    [5] C. H. Lee, S. H. Hur, Y. C. Shin, J. H. Choi, D. G. Park, and K. Kim, “ Charge-trapping device structure of SiO2/SiN/high-k dielectric Al2O3 for high-density flash memory, ” Appl. Phys. Lett. 86, 152908 (2005)
    [6] H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, C. Y. Lu, “ BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability , ” Int. Electron Devices Meeting Tech. Dig., 2005, pp. 547-550.
    [7] C. C. Yeh, W. J. Tsai, M. I. Liu, T.C. Lu, S. K. Cho, C. J. Lin, Tahui Wang, S. Pan, and Chih-Yuan Lu, “ PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory, ” Int. Electron Devices Meeting Tech. Dig., 2002, pp. 931-934.
    [8] C. C. Yeh, Tahui Wang, W. J. Tsai, T. C. Lu, M. S. Chen, Y. Y. Liao, W. Ting, J. Ku, and Chih-Yuan Lu, “ A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage Applications, ” IEEE Trans. on Electron Devices, Vol. 52, Issue 4, April 2005, pp. 541-546.
    [9] E. Lusky, Y. Shacham-Diamand, I. Blom, and B. Eitan, “ Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM Device, ” IEEE Electron Device Lett., Vol. 22, No. 11, pp. 556-558, 2001.
    [10] H. T. Lue, T. H. Hsu, M. T. Wu, K. Y. Hsieh, R. Liu, and C. Y. Lu, “ Studies of the Reverse Read Method and Second-bit Effect of 2-bit/cell Nitride-Trapping Device by Quasi-Two-Dimensional Model, ” IEEE Trans. on Electron Devices, Vol. 53, No. 1, Jan. 2006, pp. 119-125.
    [11] N. Mielke, H. P. Belgal, A. Fazio, Q. Meng, and N. Righos, “ Recovery Effects in the Distributed Cycling of Flash Memories, ” Annual Int. Reliability Physics Symp., San Jose, 2006, pp. 29-35.
    [12] M. Janai, B. Eitan, A. Shappir, E. Lucky, I. Bloom, and G. Cohen, “ Data Retention Reliability Model of NROM Nonvolatile Memory Products, ” IEEE Trans. on Device and Materials Reliability, Vol. 4, No. 3, Sep. 2004, pp. 404-415.
    [13] M. Janai and B. Eitan, “ The Kinetics of Degradation of Data Retention of Post-Cycled NROM Non-Volatile Memory Products, ” Annual Int. Reliability Physics Symp., San Jose, 2005, pp. 175-180.
    [14] W. Meyer and H. Neldel, Z. Tech. Phys,. Vol. 12, 1937, pp. 588.
    [15] Y. Yang and M. H. White, “ Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures, ” Solid-State Electronics, Vol. 44, Issue 6, June 2000, pp. 949-958.
    [16] S. J. Wrazien, Y. Zhao, J. D. Krayer, and M. H. White, “ Characterization of SONOS Oxynitride Nonvolatile Memory Devices, ” Solid-State Electronics, Vol. 47, Issue 5, May 2003, pp. 885-891.
    [17] C. C. Yeh, W. J. Tsai, T. C. Lu, H. Y. Chen, H. C. Lai, N. K. Zous, Y. Y. Liao, G. D. You, S. K. Cho, C. C. Liu, F. S. Hsu, L. T. Huang, W. S. Chiang, C. J. Liu, C. F. Cheng, M. H. Chou, C. H. Chen, T. Wang, W. Ting, S. Pan, J. Ku, and C. Y. Lu, “ Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-Type Flash Memory, ” Int. Electron Devices Meeting Tech. Dig., 2003, pp. 173-176.
    [18] H. Pang, L. Pan, L. Sun, Y. Zeng, Z. Zhang and J. Zhu, “ A New Method based on Charge Pumping Technique to Extract the Lateral Profiles of Localized Charge Trapping in Nitride, ” European Solid-State Device Research Conf., Sept. 2005, pp. 209-212.
    [19] S. S. Chung, Y.H. Tseng, C. S. Lai, Y. Y. Hsu, E. Ho, C. Chen, L. C. Peng, C.H. Chu, “ Novel Ultra-Low Voltage and High-Speed Programming/Erasing Schemes for SONOS Flash Memory with Excellent Data Retention, ” Int. Electron Devices Meeting Tech. Dig., 2007, pp. 457-460.
    [20] W. Chen, A. Balasinski, T. P. Ma, “ Lateral Profiling of Oxide Charge and Interface Traps near MOSFET Junctions, ” IEEE Trans. on Electron Devices, Vol. 40, no. 1, 1993, pp. 187-196.
    [21] A. Melik-Martirosian, T. P. Ma, “ Improved Charge-Pumping Method for Lateral Profiling of Interface Traps and Oxide Charge in MOSFET Devices, ” Int. Electron Devices Meeting Tech. Dig., 1999, pp. 93-96.
    [22] Chun Chen, Tso-Ping Ma, “ Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET's, ” IEEE Trans. on Electron Devices, Vol. 45, no. 2, 1998, pp. 512- 520.
    [23] L. Sun, L. Pan, H. Pang, U. Zeng, Z. Zhang, John Chen and J. Zhu, “ Characteristics of Band-to-Band Tunnel Hot Hole Injection for Erasing Operation in Charge-Trapping Memory, ” Jpn. J. Appl. Phys., Vol. 45, No. 4B, 2006, pp. 3179-3184.
    [24] Maarten Rosmeulen et al., “ Characterization of the Spatial Charge Distribution in Local Charge-Trapping Memory Devices using the Charge-Pumping Technique, ” Solid-State Electronics, vol. 48, 2004, pp. 1525-1530.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE