研究生: |
洪麗雯 Li-Wen Hung |
---|---|
論文名稱: |
在邏輯合成中之可重疊函數分解 Overlapping Functional Decomposition in Logic Synthesis |
指導教授: |
黃婷婷
TingTing Hwang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2000 |
畢業學年度: | 88 |
語文別: | 中文 |
論文頁數: | 44 |
中文關鍵詞: | 重疊 、函數分解 、邏輯合成 、編碼 、分離性 、非分離性 、相容級 |
外文關鍵詞: | overlapping, functional decomposition, logic synthesis, encoding, disjunctive, nondisjunctive, compatible class |
相關次數: | 點閱:2 下載:0 |
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函數分解是一種有效率的重建邏輯網路技術.過去的相關研究包括邊界組(bound set)變數的選擇,
相容級(compatible class)的編碼(encoding)等等,
大部份的問題只考慮非重疊性的結構.然而含重疊變數的電路結構事實上是比較具有彈性的,
且在某些情形下,會比非重疊性架構產生較少的面積成本.
因此在這篇論文,我們討論重疊(非分離性)變數的布林函數分解.
我們先提出一個從邊界組變數選擇出重疊變數的方法.
然後將產生的相容級指派到因重疊變數而發生的 don't care ,組成兩個 一組的相容級.
這樣的 don't care 指派,可以減少函數的相容級的個數,且增加下一級映照函數(image function)
的分解性(decomposatibilty).
最後我們提出一個相容級編碼的演算法.
然後將這種重疊函數分解計術應用到查對表式用戶現場可規劃邏輯陣列(Look-up Table based FPGA),
實驗結果證明我們的重疊性結構對於某些測試基準(test benchmark)可以有較好對應結果.
Functional decomposition is an effective technique to restructure logic networks.
Previous researches have studied how to select variables in bound set, how to encode compatible classes, etc.
However, most of previous works consider non-overlapping structures..
Circuit structures with overlapping variable are more flexible and may have lower area costs than the non-overlapping
structures in some cases.
Therefore, in this paper, we will study nondisjunctive functional decompositions for Boolean functions.
We first propose an algorithm to select overlapping variables from the bound set of a function.
After the overlapping variable selection algorithm is applied, the compatible classes are paired to assign don't cares.
The objectives of the don't care assignment heuristic are to reduce the compatible classes and to increase the decomposability
of the image function that will be decomposed in the next level.
Finally, we proposed an algorithm to improve the compatible class encoding algorithm proposed in HYDE.
Then, we apply this nondisjunctive functional decomposition technique to look-up table (LUT) based FPGA synthesis.
The experimental results show that our overlapping approach can lead to better mapping results on some particular cases of benchmarks.
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