現今使用邏輯掃描測試的電路越來越普遍，如何降低測試所需的成本也是近年來相當熱門的研究重點。此篇論文將介紹一種新的測試方法，稱作”間接存取之瞄測試”。和傳統測試機台不同，使用封包傳遞的方式，透過無線通道將測試資料送到測試電路進行測試。這種先在測試端存取測試資料在進行測試的方法雖較使用傳統測試機台費時，但它所帶來的好處是擁有幾近無限的測試資料存放空間，尤其是在測試資料越來越龐大的現今，傳統測試機台的測試資料存放空間非常容易就被使用殆盡。除此之外，我們還要在這篇論文中提出幾項增進測試效率的技術，他們分別是：針對PI(Primary Input)的測試資料進行壓縮、使用更有效率的動態邊界封包以及混合式的測試結果壓縮方式。在實驗結果中，針對某個155K邏輯閘的電路，我們可以達到加快測試速度50倍的加速效果。
以下為論文各章節內容的摘要：
第一章：簡單介紹間接存取測試的概念和研究動機，使用間接存取測試平台進行掃描測試的好處以及將會面臨的挑戰。
第二章：坐一個完整對於間接存取掃描測試的架構介紹，以及使用到的相關技術介紹。最後是和傳統直接存取平台的比較。
第三章：解說如何在間接存取測試平台進行有效綠的掃描測試，其相關的技術及改進將在這章做詳細的介紹。
第四章：此章將會提出一個具有互動是的掃描測試流程於后羿測試平台，將更有效率的進行除了掃描測試，更能增加針對進行診斷時的解析度。
第五章：所有的實驗結果。
第六章：結論。

In this thesis, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited test memory – a highly desirable property since the large volume of test data today could easily blow up a traditional ATE’s test memory. In addition to demonstrating the feasibility of this new paradigm, we also show that its efficiency can be substantially improved by three schemes; i.e., primary input (PI) data encoding, dynamic packet formatting and hybrid compaction method. For a design with 155K gates, the speed-up achieved can be more than 50X.

[1] C.-W. Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T. Hsing, “The HOY Tester – Can IC Testing Go Wireless?” Proc. Int’l Symp. On VLSI Design, Automation, and Test (VLSI-DAT), pp. 183-186, Apr. 2006.
[2] P.-K. Chen, Y.-T.Hsing, and C.-W. Wu, “On Feasibility of HOY – A Wireless Test Methodology for VLSI Chips and Wafers,” Proc. Int’l Symp. On VLSI Design, Automation, and Test (VLSI-DAT), pp. 243-246, Apr. 2006.
[3] K.-J. Lee, J. J. Chen, and C. H. Huang, “Using a Single Input to Support Multiple Scan Chains,” Proc. of Int’l Conf. on Computer-Aided Design, pp. 74-78, Nov. 1998.
[4] M. H. Tehranipour, M. Nourani, and K. Chakarbarty, “Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression,” Proc. of Design, Automation and Test in Europe Conf. (DATE), pp. 1284-1289, 2004.
[5] M. Nourani, and M. Tehranipour, “RL-Huffman Encoding for Test Compression and Power Reduction in Scan Applications,” ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 91-115, 2005.
[6] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherje, "Embedded Deterministic Test,” IEEE Trans. on Computer-Aided Design, vol. 23, no. 5, pp. 776-792, 2004.
[7] L.-T. Wang, X. Wen, H. Furukawa, F.-S. Hsu, S.-H. Lin, S.-W. Tsai, K. S. Abdel-Hafez, and S. Wu, “VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Proc. of Int’l Test Conf., pp. 916-925, Oct. 2004.
[8] A. Al-Yamani, E. Chmelar, and M. Grinchuck, ” Segmented addressable scan architecture,” proc. of VLSI Test Symp., pp. 405 - 411, May 2005.
[9] C.-W. Tzeng and S.-Y. Huang, "UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting," IEEE Design & Test of Computers, Vol. 25, No. 2, pp. 132-140, Mar.-Apr. 2008.
[10] C. W. Branson, “Integrating Tester Pin Electronics,” IEEE Design & Test of Computers, Vol. 7, No. 2, pp. 4-14, Apr. 1990.
[11] T. Rockoff, “The Rise and Fall of the ATE Industry,” Proc. Of Int’l Test Conf., pp. 1154-1179, 1998.
[12] M. Nahvi and A. Ivanov, “Indirect Test Architecture for SoC Testing,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 7, pp. 1128-1142, 2004.
[13] N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, and T. W. Williams, “Changing The Scan Enable During Shift,” Proc. of VLSI Test Symp., pp. 73-78, Apr. 2004.
[14] S. Mitra and K. S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Tran. on Computer-Aided Design, vol. 23, no. 3, Mar. 2004
[15] Z. Stanojevic, R. Guo, S. Mitra, and S. Venkataraman,” Enabling Yield Analysis with X-Compact,” Proc. of Int’l Test Conference, pp. 163-173 Nov. 2005
[16] T. W. Williams and W. Daehn, “Aliasing errors in multiple input signature analysis registers,” Proc. of Test Conference, European Test Conference, 1989., pp. 338-345, Apr. 1989.
[17] T.-W. Ko, Y.-T. Hsing, C.-W. Wu, and C.-T. Huang, "Stable Performance MAC Protocol for HOY Wireless Tester under Large Population," Proc. of VLSI Design, Automation, and Testing (VLSI-DAT), pp. 1-4, Apr. 2007.
[18] K. Brion and B. Thomas, “Use of MISRs for Compression and Diagnostics,” International Test Confernce, Cadence Design Systems, pp. 733– 743, Nov. 2005.
[19] L.-T. Wang, C.-W. Wu, and Xiaoqing Wen, “VLSI Test Principles and Architectures : Design for Testability”, Elsevier Morgan Kaufmann Publishers, 2006.
[20] M. Abramovici, M. A. Breuer, and A. D. Friedman , “Digital Systems Testing and Testable Design,” IEEE Press, 1990.
[21] CIC Referenced Flow for Cell-based IC Design, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.