快閃記憶體（Flash Memory）是目前消費性電子產品中廣泛應用到的元件。在對快閃記憶體大量儲存空間的需求下，多層單元（Multi-Level Cell，MLC）快閃記憶體成為一項受歡迎的只需增加些許成本而增加儲存容量的解決方案。然而由於快閃記憶體有限的寫入/抹除（program/erase）次數的限制，如何隨著時間而維持可靠度變成了一項重要的議題。現今，錯誤更正編碼（Error Correction Coding，ECC）被廣泛運用來增加快閃記憶體的耐用性與可靠度。不同的錯誤更正方案會使得備援記憶體的使用效率不同，因此導致快閃記憶體的耐用性與可靠度的不同。

在這篇論文中，我們提出了一個將焦點放在快閃記憶體控制器上常用的BCH碼（Bose-Chaudhuri-Hocquenghem codes），並提出一個適用於NAND型快閃記憶體之適應性編碼率錯誤更正系統設計，以增加快閃記憶體的耐用性與可靠度。數種模式的BCH碼被設計為具有不同的錯誤更正能力並產生不同長度的檢查位元。當原先設計的備援記憶體大小不足以儲存檢查位元時，為了要儲存這些「額外」的檢查位元，我們便需要一種將非備援記憶體當作備援記憶體使用的記憶體儲存策略。此外，本文也展示了一種可設定組態的線性回饋移位暫存器（Linear feedback shift register, LFSR）設計，用以節省可變錯誤更正能力的BCH編碼器的面積。有了本文提出的錯誤更正方案，快閃記憶體控制器便能在依原先非備援記憶體容量設計的錯誤更正碼已經無法應付毀損的記憶單元數量的情況下，透過犧牲部分原先設計用來儲存使用者資料的記憶空間，來維持記憶體的可用性。

Flash memory is one of the most widely used cores in current consumer products. Given the high demand of mass storage,multi-level cell (MLC) flash has become a cost-effective solution to increase the storage capacity. However, due to limited program/erase cycles of flash, how to maintain the reliability over time is an important issue. Nowadays, error correction coding (ECC) is widely used to enhance flash memory endurance and reliability. Different error correction schemes may lead to different efficiency of redundant memories that store parity bits, and thus different endurance and reliability for a specific flash memory.

In this work, we focus on the Bose-Chaudhuri-Hocquenghem (BCH) codes for flash memory, and propose an adaptive-rate error correction scheme that is implemented on the memory controller. Several modes of BCH codes are designed to give different correction capabilities, which require different lengths of parity bits. To store the "extra" parity bits when the originally designed redundant memory capability is not enough for the parity bits, a storage strategy that stores the parity bits in the main memory array is needed. Besides, a configurable linear feedback shift register (LFSR) is shown here to reduce the area of BCH encoder, in which correction capability is changeable. With this error correction scheme, flash memory can trade user storage space for higher error correction capability to keep it usable even when the initially designed ECC can no longer cover the errors.

[1] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories, Kluwer Academic Pub-
lishers, Boston, 1999.
[2] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory”, Pro-
ceedings of the IEEE, vol. 91, no. 4, pp. 489–502, April 2003.
[3] D. Byeon, S. Lee, Y. Lim, J. Park, W. Han, P. Kwak, D. Kim, D. Chae, S. Moon, S. Lee,
H. Cho, J. Lee, M. Kim, J. Yang, Y. Park, D. Bae, J. Choi, S. Hur, and K. Suh, “An 8Gb
multi-level NAND flash memory with 63nm sti CMOS process technology”, in Proc. IEEE
Int’l Solid-State Cir. Conf. (ISSCC), 2005, pp. 46–47 Vol. 1.
[4] Semiconductor Industry Association, “International technology roadmap for semiconductors
(ITRS), 2007 edition”, Dec. 2007.
[5] J. Agin, H. Boyce, and T. Trexler, “Overcoming test challenges presented by embedded flash
memory”, in Proc. Int’l Electronics Manufacturing Technology Symp. (IEMT), July 2003, pp.
197–200.
[6] Samsung Electronics, “K9XXG08UXA 512M x 8 Bit / 1G x 8 Bit NAND Flash Memory”,
http://www.samsung.com/, 2006.
[7] Samsung Electronics, “K9F8G08UXM 1G x 8 Bit/ 2G x 8 Bit NAND Flash Memory”,
http://www.samsung.com/, 2007.
[8] ST Microelectronics, “4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memo-
ries”, http://www.st.com/, 2007.
[9] ST Microelectronics, “8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND
Flash memory”, http://www.st.com/, 2007.
[10] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Archi-
tectures, Elsevier (Morgan Kaufmann), San Francisco, 2006.
[11] S. Gregori, A. Cabrini, O. Khouri, and G. Torelli, “On-chip error correcting techniques for
new-generation flash memories”, Proc. of the IEEE, vol. 91, no. 4, pp. 602–616, Apr. 2003.
[12] A. Silvagni, G. Fusillo, R. Ravasio, M. Picca, and S. Zanardi, “An overview of logic archi-
tecture inside flash memory devices”, Proc. of the IEEE, vol. 91, no. 4, pp. 569–580, Apr.
2003.
[13] D. Rossi, C. Metra, and B. Ricco, “Fast and compact error correcting scheme for reliable
multilevel flash memories”, in Proc. IEEE Int’l Workshop on Memory Technology, Design
and Testing (MTDT), 2002, pp. 27–31.
[14] S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, Prentice-
Hall Inc., Englewood Cliffs, NJ, second edition, 2004.
[15] Tood K. Moon, Error Correction Coding: Mathematical Methods and Algorithms, John Wi-
ley & Sons, New York, 2005.
[16] Xu Youzhi, “Implementation of Berlekamp-Massey algorithm without inversion”, Commu-
nications, Speech and Vision, IEE Proceedings I, vol. 138, pp. 138–140, 1991.
[17] H. Burton, “Inversionless decoding of binary BCH codes”, IEEE Trans. on Information The-
ory, vol. 17, pp. 464–466, 1971.
[18] Yanni Chen and K.K. Parhi, “Small area parallel Chien search architectures for long BCH
codes”, IEEE Trans. on VLSI Systems, vol. 12, pp. 545–549, 2004.
[19] J. Cho and W. Sung, “Strength-reduced parallel Chien search architecture for strong bch
codes”, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol.
55, pp. 427–431, 2008.
[20] J. L. Massey, “Shift-register synthesis and BCH decoding”, IEEE Trans. on Information The-
ory, vol. 15, pp. 122–127, 1969.
[21] R. Chien, “Cyclic decoding procedures for Bose-Chaudhuri-Hocquenghem codes”, IEEE
Trans. on Information Theory, vol. 10, pp. 357–363, 1964.
[22] R. Micheloni, R. Ravasio, A. Marelli, E. Alice, V. Altieri, A. Bovino, L. Crippa, G. Di Mar-
tino, L. D’Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta,
A. Prisco, G. Ragone, M. Romano, M. Sangalli, P. Sauro, M. Scotti, and S. Won, “A 4Gb
2b/cell NAND flash memory with embedded 5b BCH ECC for 36MB/s system read through-
put”, in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), 2006, pp. 497–506.
[23] Open NAND Flash Interface Workgroup, “Open NAND flash interface (ONFi) specification
Rev2.0”, http://www.onfi.org/, 2008.