While Network-on-Chip (NoC) remains the more scalable and flexible infrastructure to interconnect a large number of processing elements (PEs) and memory subsystems, power
consumption will also grows linearly with the number of components in the system including routers, switches and buffers. Under limited power budget, it would be necessary to allow DVFS (Dynamic Voltage and Frequency Scaling) type of control over NoC under user’s specified constraints of timing. In this paper, we conduct an initial study on the power management by assuming that frequencies of individual links of NoC can be adjusted according to different condition of traffic requirements. An approximate model is proposed to estimate the energy, bandwidth and latency under different frequency settings of NoC system. We then use the model to optimize energy consumption of a specific traffic pattern under timing constraints.

在系統晶片中，連接大量的處理元件和記憶體子系統時，晶片內網路一直是較具伸縮性和彈性的基礎架構。也因此在系統中的路由器、交換器和鏈結所消耗的能量會隨著組件的數量增加而線性地成長。又因為晶片運作時有功率上限的限制，必須以動態電壓與頻率調節來控制晶片內網路來節省能量，並在此同時將晶片內網路的時序維持在使用者的限制之內。在這篇論文中，我們假設晶片內網路的每個獨立鏈結的運作頻率可以根據不同的流量需求而作調整，並導引出一個電源管理方法的初步研究。我們提出了一個用來估計晶片內網路能量消耗、頻寬和延遲時間的近似模型。之所以需要近似模型，主要是因為精準的模型至少必須使用到暫存器傳輸級設計來作模擬，而此層級的設計在模擬時間上過長，無法滿足我們快速估計晶片內網路能量消耗的需求。運用此模型，我們可以在具體的交通流量模式下，最佳化晶片內網路的能量消耗，並保持時序在限制的值之內。在這裡我們使用模擬退火來作為最佳化能量消耗的演算法，只是為了找出動態電壓與頻率調節方法可能為晶片整體功耗帶來的好處，並未對該演算法做最佳化。實作時仍可考慮其它最佳化演算法，並不限於模擬退火演算法。

[1] Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Anh Tran, Zhibin Xiao, Eric Work, Jeremy Webb, Paul Mejia, Bevan Baas, ”A 167-Processor Computational Platform in 65 nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 4, pp. 1130-1144, April 2009.
[2] Andrew Kahng, Bin Li, Li-Shiuan Peh and Kambiz Samadi, ”ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration” In Proceedings of Design Automation and Test in Europe (DATE), Nice, France, April 2009.
[3] Vangal, S.R.; Howard, J.; Ruhl, G.; Dighe, S.; Wilson, H.; Tschanz, J.; Finan, D.; Singh, A.; Jacob, T.; Jain, S.; Erraguntla, V.; Roberts, C.; Hoskote, Y.; Borkar, N.; Borkar, S.;, ”An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of , vol.43, no.1, pp.29-41, Jan. 2008.
[4] Teodorescu, R.; Torrellas, J.; , ”Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors,” Computer Architecture, 2008. ISCA ’08. 35th International Symposium on , vol., no., pp.363-374, 21-25 June 2008.
[5] Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen. 2010. Power and performance optimization of voltage/frequency island-based networks-onchip using reconfigurable synchronous/bi-synchronous FIFOs. In Proceedings of the 7th ACM international conference on Computing frontiers (CF ’10). ACM, New York, NY,
USA, 267-276. 29
[6] Bell, S.; Edwards, B.; Amann, J.; Conlin, R.; Joyce, K.; Leung, V.; MacKay, J.; Reif, M.; Liewei Bao; Brown, J.; Mattina, M.; Chyi-Chang Miao; Ramey, C.; Wentzlaff, D.;
Anderson, W.; Berger, E.; Fairbanks, N.; Khan, D.; Montenegro, F.; Stickney, J.; Zook, J.; , ”TILE64 - Processor: A 64-Core SoC with Mesh Interconnect,” Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International , vol., no., pp.88-598, 3-7 Feb. 2008.
[7] Arnab Banerjee, Robert Mullins, and Simon Moore. 2007. A Power and Energy Exploration of Network-on-Chip Architectures. In Proceedings of the First International
Symposium on Networks-on-Chip (NOCS ’07). IEEE Computer Society, Washington, DC, USA, 163-172.
[8] William J. Dally and Brian Towles. 2001. Route packets, not wires: on-chip inteconnection networks. In Proceedings of the 38th annual Design Automation Conference (DAC
’01). ACM, New York, NY, USA, 684-689.