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研究生: 李銘中
Lee, Ming-Chun
論文名稱: 以積體電路實現可擴充型擴散網路
The Design of Scalable Diffusion Network in VLSI
指導教授: 陳新
Chen, Hsin
口試委員: 謝志成
蔡嘉明
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 100
語文別: 中文
論文頁數: 93
中文關鍵詞: 擴散網路可擴充性
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  • 在醫療領域上,生醫晶片可應用於生理訊號的辨識,舉例來說,將神經微電極陣列植入於生物體內,然後對生物體的神經組織進行長期量測,並利用晶片系統辨識生理訊號,再給予生物體適當的刺激或控制人工義肢等電子輔具,藉以恢復病患基本的生活能力。由於生理訊號具有變異性,若想要辨識生物體的高雜訊生理訊號,晶片系統便需要擁有容忍高雜訊的能力。為了使晶片系統順利的辨識高雜訊的生理訊號,所以晶片系統所採用的演算法是由Movellan等人所發表的擴散網路(Diffusion Network)機率型演算法,此演算法可運用自身的隨機性以概括訊號的變異而得出有意義的時變資訊,因此,擴散網路能夠辨識充滿漂移與雜訊的生理訊號,例如辨識心跳訊號。
    在擴散網路內,任一神經細胞對所有的神經細胞皆有專屬的連接線。對於擁有此種特性的網路,可擴充性在過去的文獻中並未解決,所以在本文中提出一個可擴充型架構。首先,透過解決每一個神經細胞的突觸數量如何隨著欲處理訊號維度的提高而增加,以及思考神經細胞與神經細胞之間的連線問題,逐步設計適用於擴散網路的可擴充型系統架構。在完成可擴充型系統架構後,接下來便開始設計一個神經細胞的實際電路,在設計的過程需要考慮數值上的參數範圍與電路上的數值範圍之間的關係,然後擴散網路的電路系統便能藉著多個神經細胞的電路連接而組成,再進行電路模擬以驗證擴散網路的電路系統是否能夠成功重建訊號。最後,比較可擴充型擴散網路晶片的實際量測結果與理想電路的模擬結果,接著分析產生誤差的原因,然後提出解決方案以使可擴充型擴散網路晶片能夠成功重建訊號。


    誌謝 I 摘要 II Abstract III 章節目錄 IV 圖目錄 VI 表目錄 X 第一章 緒論 1 1.1 研究背景 1 1.2 研究目的 2 1.3 章節簡介 3 第二章 文獻回顧 5 2.1 可擴充性系統架構簡介 5 2.2 擴散網路簡介 13 2.3 擴散網路神經元在超大型積體電路的實現 21 第三章 可擴充性擴散網路系統架構 23 3.1 單晶片內系統架構 24 3.2 多晶片間系統架構 30 第四章 擴散網路神經元的內部電路架構與模擬 33 4.1 電流乘法器電路架構與模擬 34 4.2 可變電阻電路架構與模擬 38 4.3 S函數計算電路架構與模擬 42 4.4 雜訊產生器電路架構 47 第五章 擴散網路晶片系統模擬結果 50 5.1 運用擴散網路晶片系統重建訊號 50 5.2 重建訊號模擬 53 5.2.1 重建弦波 53 5.2.2 重建分支曲線 55 5.2.3 重建心電圖 59 5.2.4 重建希臘字母 61 5.3 擴散網路晶片的佈局與腳位配置 64 第六章 擴散網路晶片系統量測結果 70 6.1 電路量測 70 6.1.1 電流乘法器 70 6.1.2 可變電阻電路 76 6.1.3 S函數計算電路 80 6.2 重建訊號量測設置 85 第七章 結論 89 7.1 研究總結 89 7.2 未來發展的方向 90 參考文獻 91

    [1] J. R. Movellan, P. Mineiro, and R. J. Williams, “A Monte-Carlo EM approach for partially observable diffusion processes: Theory and applications to neural networks,” Neural Computation, vol. 14, no. 7, pp. 1507-1544, 2002.
    [2] Y. Hsu, T. Chiu, and H. Chen, “Real-time recognition of continuous-time biomedical signals using the diffusion network,” in Proceedings of the International Joint Conference on Neural Networks, pp. 2628-2633, 2008.
    [3] E. K. Lee and P. G. Gulak, “A CMOS field-programmable analog array,” in IEEE Journal of Solid-State Circuits, vol. 26, no. 12, pp. 1860-1867, December 1991.
    [4] D. R. D’Mello and P. G. Gulak, “Design approaches to field-programmable analog integrated circuits,” Analog Integrated Circuits and Signal Processing, vol. 17, no. 1, pp. 7-34, September 1998.
    [5] K. Papathanasiou, T. Brandtner, and A. Hamilton, “Palmo: pulse-based signal processing for programmable analog VLSI,” in IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 6, pp. 379-389, June 2002.
    [6] L.C. Gouveia, T.J. Koickal, and A. Hamilton, “An asynchronous spike event coding scheme for programmable analog arrays,” in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1364-1367, May 2008.
    [7] V. George and J. Rabaey, “Low-Energy FPGAs: Architecture and Design,” Norwell, MA: Kluwer, 2001.
    [8] Microsemi Corporation, “Accelerator Series FPGAs - ACT 3 Family,” Microsemi SoC Products Group, http://www.actel.com/documents/ACT3_D S.pdf, 2011.
    [9] Actel Corporation, “SX Family FPGAs Datasheet,” Microsemi SoC Products Group, http://www.actel.com/documents/A54SX_DS.pdf, 2006.
    [10] M. Butts and J. Batcheller, “Method of using electronically reconfigurable logic circuits,” US Patent 5,036,473, 1991.
    [11] S. Hauck, “The roles of FPGAs in reprogrammable systems,” Proceedings of the IEEE, vol. 86, no. 4, pp. 615-638, April 1998.
    [12] M. Sivilotti, “Wiring considerations in analog VLSI systems, with application to field-programmable networks,” Ph.D. dissertation, California Institute of Technology, 1991.
    [13] M. Mahowald, “VLSI analogs of neuronal visual processing: A synthesis of form and function,” Ph.D. dissertation, California Institute of Technology, 1992.
    [14] K. Boahen, “Point-to-point connectivity between neuromorphic chips using address events,” in IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 416-434, May 2000.
    [15] D. Chen, Y. Li, D. Xu, J. G. Harris, and J. C. Principe, “Asynchronous biphasic pulse signal coding and its CMOS realization,” in International Symposium on Circuits and Systems, 2006.
    [16] M. Rastogi, V. Garg, and J. G. Harris, “Low power integrate and fire circuit for data conversion,” in IEEE International Symposium on Circuits and Systems, pp. 2669-2672, 2009.
    [17] T. Koickal, L. Gouveia, and A. Hamilton, “Bio-inspired Event Coded Configurable Analog Circuit Block,” Evolvable Systems: From Biology to Hardware, LNCS 5216, Berlin: Springer-Verlag, pp. 285-295, 2008.
    [18] M.-R. Chu, “Design of the Neuron Circuit for the Diffusion Network in VLSI,” Master's thesis, National Tsing Hua University, Taiwan, 2006.
    [19] C.-H. Chien, “A Stochastic System on a Chip Basing on Diffusion Network,” Master's thesis, National Tsing Hua University, Taiwan, 2008.
    [20] C. Sawigun and W.A. Serdijn, “A nano-power class-AB current multiplier for energy-based action potential detector,” European Conference on Circuit Theory and Design, pp. 417-420, 23-27 August 2009.
    [21] S.-C. Liu, J. Kramer, G. Indiveri, T. Delbrück, and R. Douglas, “Analog VLSI: Circuits and Principles,” MIT Press, 2002.
    [22] J. A. Gómez Galán, M. P. Carrasco, M. Pennisi, A. L. Martin, R. González Carvajal, and J. Ramirez-Angulo, “Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity,” ETRI Journal, vol. 31, no. 5, October 2009.
    [23] G. Cauwenberghs, “Delta-sigma cellular automata for analog VLSI random vector generation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 3, pp. 240-250, 1999.

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