具有冗餘位元和非整數分離式電容陣列的十二位元連續漸進式類比數位轉換器

簡易檢索 / 詳目顯示

回結果列表

研究生：	蘇炫峰 Su, Syuan-Fong
論文名稱：	具有冗餘位元和非整數分離式電容陣列的十二位元連續漸進式類比數位轉換器 12-bit SAR ADC with redundancy using non-integer and split capacitive-array DAC
指導教授：	朱大舜 CHU, TA-SHUN
口試委員:	吳仁銘 WU, JEN-MING 王毓駒 Wang, Yu-Jiu
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	中文
論文頁數：	88
中文關鍵詞：	類比數位轉換器、冗餘位元、連續漸進式類比數位轉換器、非整數分離式電容陣列
外文關鍵詞：	non-integer, split capacitive-array DAC
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

近幾年來物聯網發展非常的迅速，物聯網可處理資料、遠程地收集環境中各種的資料和利用網路取回這些寶貴的資料。為了感測環境中的資料，類比數位轉換器為此系統中不可或缺的電路。在現代5G連接互聯網的情況下，物聯網的應用通常需要無線裝置，而低功耗的特性為無線裝置中重要的考量。在低功耗的考量中，連續漸進式類比數位轉換器為最近較流行的選擇。

本論文實現了一個高速帶冗餘位連續漸進式類比數位轉換器，在每秒一點二億次取樣的速度下，使用了帶冗餘位演算法達到速度上的優化，並且提出一個新穎的電容矩陣架構縮小其面積且降低電容的耗能。直接切換邏輯的應用不但提升了速度，也使電容有更多的穩定時間。此類比數位轉換器具有高速、低面積的特性，可以用於時序交錯式的類比數位轉換器，透過通道並聯的方式，達到速度上的提升。

本論文之十二位元連續漸進式類比數位轉換器使用台積電65奈米CMOS製程來設計，在1.2 V供電以及每秒取樣一點二億次操作下，本電路可達到軌對軌輸入訊號的振幅為2.2 V，模擬結果為訊號與雜訊諧波比可達到72.6 dB，相當於有效位元為11.765，DNL為+0.1/-0.1LSB，INL為+0.16/-0.22 LSB，平均消耗功率為7.313mW。

The Internet of Things (IoT) has developed rapidly in recent years. IoT is a method that processes the data, collects environmental data remotely, and retrieves the results over the internet. To sense environmental data in this situation, analog-to-digital converters (ADCs) is an indispensable circuit in the system. In the era of modern 5G access to the internet, IoT applications typically require wireless devices. Low power consumption is a key feature of wireless devices. For this key point, the successive approximation register (SAR) ADC has become a popular choice.

In the thesis, we have proposed a high-speed SAR ADC with the redundancy algorithm to speed up the conversion rate. A novel capacitor array is proposed to scale down the area and the power consumption. Direct-switched SAR Logic not only speed up the conversion rate but also make cap array more time to stable. This ADC has high speed performance and low area cost. It can be applied to Time-interleaved ADC. The operation speed will be enhanced by channel shunting.

The 12 bits SAR ADC was fabricated in the TSMC 65 nm CMOS process. At 1.2 V supply voltage and 120 Ms/s sampling rate, this design achieves the full rail-to-rail input swing is 2.2 V peak to peak and signal to noise and distortion ratio (SNDR) 72.6 dB, equivalent to the effective number of bits (ENOB) 11.765. The peak DNL values are -0.1 to +0.1 LSB and the peak INL values are -0.16 to +0.22 LSB. The average power consumption is 7.313 mW.

摘要    i
Abstract    ii
目錄    iii
表目錄    viii
圖目錄    ix
第一章  簡介    1
1   研究動機    1
2   論文章節組織    2
第二章  研究背景以及相關研究介紹    3
1  類比數位轉換器參數    3
1.1  專有名詞    3
1.1.a  奈奎斯特準則(Nyquist criterion)    3
1.1.b  取樣率(Sampling Rate)    3
1.1.c  解析度(Resolution)    3
1.1.d  最小解析度(Least Signification Bit)    4
1.1.e  量化誤差(Quantization Error)    4
1.2  靜態參數    5
1.2.a  偏移誤差(Offset Error)     5
1.2.b  增益誤差(Gain Error)     6
1.2.c  差動非線性度(Differential Nonlinearity)     6
1.2.d  積分非線性度(Integral Nonlinearity)     7
1.2.e  遺失碼(Missing Codes)     7
1.3  動態參數    8
1.3.a  訊號對雜訊比(Signal-to-Noise Ratio)    8
1.3.b  訊號對雜訊失真比(Signal-to-Noise and Distortion Ratio)  9
1.3.c  有效位元數(Resolution and Effective Number of Bits)    9
1.3.d  無雜訊動態範圍(Spurious-Free Dynamic Range)    9
1.3.e  動態範圍(Dynamic Range)    9
1.3.f  總諧波失真(Total Harmonic Distortion)    10
1.3.g  優值(Figure of Merit)    10
2  類比數位轉換器的架構    10
2.1  快閃式類比數位轉換器(Flash ADC)    11
2.2  導管式類比數位轉換器(Pipeline ADC)    12
3  連續漸進式類比數位轉換器(SAR ADC)概述    12
3.1  SAR ADC操作原理    12
3.2  SAR ADC基礎技術原理    13
3.2.a  單端與雙端(Single-Ended Signal VS. Differential Signal) 13
3.2.b  下板取樣與上板取樣(Bottom-Plate Sampling VS. Top-Plate Sampling) 14
3.2.c  同步與非同步(Synchronous VS. Asynchronous)    15
3.2.d  電荷重新分配(Charge Redistribution)    16
3.3  SAR ADC切換過程    17
3.3.a  傳統式電容切換法
(Conventional Capacitor Switching Procedure)    17
3.3.b  單調式電容切換法
(Monotonic Capacitor Switching Procedure)    18
3.3.c  基於共模電壓電容切換法
(VCM-Based Capacitor Switching Procedure)    19
3.3.d  電容拆半切換法
(Splitting-Capacitor Switching Procedure)    20
3.4  電容切換法能量分析    21
第三章  高速帶冗餘位連續漸進式類比數位轉換器    22
1  SAR ADC速度上的限制    22
1.1  比較時間(Comparison Time)    23
1.2  C-DAC穩定時間與比較器重置所需時間
(C-DAC Settling Time and Comparator Resetting Time)    24
1.3  數位邏輯閘電路延遲(Digital Circuit Gate Delay)    25
2  SAR ADC 基本與進階演算法........27
2.1  二進制搜尋法(Binary Search Algorithm)........27
2.2  帶冗餘位演算法(Redundancy Algorithm)......29
2.3  二進制延伸重新組合搜尋法
(Binary-scaled Recombination Weighting Algorithm) .....32
2.4  非二進制搜索法(Non-binary Search Algorithm)......33
3  C-DAC參考電壓穩定度(The stability of Reference Voltage) .....33
第四章  一個12-bit 120-Ms/s SAR ADC之設計    35
1  取樣及保持電路(Sample and Hold Circuit)    35
1.1  電路原理    36
1.2  設計考量    36
1.2.a  頻寬(Bandwidth)     37
1.2.b  MOS開關的導通電組(On-Resistance of MOS Switch)    38
1.2.c  熱雜訊(kT/C Noise)    39
1.2.d  電荷注入效應(Charge Injection)     40
1.2.e  時脈饋入效應(Clock Feedthrough)    42
1.2.f  取樣抖動(Sampling Jitter)    43
1.3  電路實作    43
1.4  模擬結果    46
2  比較器(Comparator)    48
2.1  電路原理    48
2.2  設計考量    52
2.2.a  操作速度(Speed)    52
2.2.b  準確度(Accuracy)    52
2.2.c  輸入參考偏移(Input Referred Offset)    53
2.2.d  回饋雜訊(Kick-back noise)    54
2.3  電路實作    56
2.4  模擬結果    58
3  電容式數位類比轉換器矩陣(Capacitive DAC)     61
3.1  寄生電容(Parasitic Capacitance )     62
3.2  電容不匹配(Mismatch of Capacitors)    62
3.3  穩定錯誤(Settling Error)    63
3.4  電容陣列權重(Capacitor Array Weighting)    64
3.5  電容大小    68
4     非同步SAR邏輯(Asynchronous SAR Logic )    69
5     參考電壓緩衝電路(Reference Voltage Buffer)    77
5.1  設計考量與電路實現    78
6  連續漸進式類比數位轉換器模擬結果    80
6.1  動態參數    80
6.2  靜態參數與功耗    81
第五章  結論與未來發展    84
參考文獻    85

                                

[1] B. Goll, et al., Comparators in Nanometer CMOS Technology, Berlin, Germany: Springer, 2015.
[2] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Liu, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. solid-state circuit, vol.45, no.4, pp.731-740, April 2010.
[3] Tertulien Ndjountche, CMOS Analog Integrated Circuits High-speed and Power-efficient Design, New York, CRC Press, 2011.
[4] T. Kobayashi et al., ‘‘A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,’’ IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523–527, April 1993.
[5] B. Wicht et al., “Yield and speed optimization of a latch-type voltage sense amplifier,”IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul. 2004.
[6] P. Nuzzo, et al., “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits and Syst. I, vol. 55, no. 6, pp. 1441–1454, Jun. 2008.
[7] Asad Abidi et al., “Understanding the regenerative comparator circuit,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2014, pp. 1–8.
[8] T. Ogawa et al., “SAR ADC algorithm with redundancy,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Nov. 2008, pp. 268–271.
[9] W. Liu et al., “A 12b 22.5/45MS/s 3.0mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 380−381.
[10] W. Liu et al., “A 12-bit 50-MS/s 3.3mW SAR ADC with background digital calibration,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2012.
[11] Albert. H. Chang et al., “A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration” in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), 2013, pp. 109–112.
[12] Chun-Cheng Liu, Che-Hsun Kuo, and Ying-Zu Lin, A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS
[13] C.-k. Lee, W. Kim, H. Kang, and S.-T. Ryu, “A replica-driving technique for high performance SC circuits and pipelined ADC design,” IEEE Trans. Circuits Syst. II, vol. 60, no. 9, pp. 557–561, Sep. 2013.
[14] R. Vitek, et al., “A 0.015 mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5 b/step redundancy and digital metastability correction,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2012, pp.1–4.
[15] Design of a Reference Voltage Buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
[16] F.Kuttner et al., “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-µm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2002, pp. 176−177.
[17] S.-W. M. Chen et al., “A 6-bit 600-MS/s 5.3mW asynchronous ADC in 0.13 µm CMOS,”
[18] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,”in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Dec. 2010, pp. 196-199.
[19] H.-Y. Tai et al., “A 3.2fJ/c.-s. 0.35 V 10 b 100 kS/s SAR ADC in 90 nm CMOS,” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, Jun. 2012, pp. 92–93.
[20] Toru Okazaki, et al., “A Design Technique for a High-speed SAR ADC Using Non-binary Search Algorithm and Redundancy,”in Proc. IEEE Asia Pacific Microwave Conf. (APMC), Dec. 2013, pp. 506-508.
[21] Hyeok-Ki Hong et al., “A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2012, pp. 1−4.
[22] Guan-Ying Huang, et al “A 10-bit 200MS/s 0.82mW SAR ADC in 40-nm CMOS,” A-SSCC, p. 289(2013).
[23] Hanie Ghaedrahmati, and Jianjun Zhou "160 MS/s 20MHz bandwidth third-order noise shaping SAR ADC," Electronic Letters, p128(2018)
[24] Prakash Harikumar and J Jacob Wikner, "Design of a reference voltage buffer for a 10-bit 50MS/s SAR ADC in 65nm CMOS," ISCAS, p. 249 (2015).
[25] M. Dessouky and A. Kaiser, “Input switch configuration for rail-to-rail operation of switched opamp circuits,” Electronic Letter, vol. 35, pp. 8–10, Jan. 1999.
[26] B. Razavi, Design of Analog CMOS Integrated Circuits, International ed., Boston: McGraw-Hill, 2010.
[27] M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter Analysis of High-Speed Sampling Systems,” IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 220-224, 1990.
[28] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl and B. Nauta, "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, 2007, pp. 314-605.102
[29] A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," in IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
[30] G. Huang and P. Lin, "A fast bootstrapped switch for high-speed high-resolution A/D converter," 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, 2010, pp. 382-385.
[31] H. Chen, L. He, H. Deng, Y. Yin and F. Lin, "A high-performance bootstrap switch for low voltage switched-capacitor circuits," 2014 IEEE International Symposium on Radio-Frequency Integration Technology, Hefei, 2014, pp. 1-3.
[32] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
[33] Kobayashi, Tsuguo, et al. "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture." IEICE transactions on electronics 76.5 (1993): 863-867.
[34] P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 541-545, July 2006, doi: 10.1109/TCSII.2006.875308.
[35] M. v. Elzakker, E. v. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” IEEE ISSCC Dig. Tech. Papers, February, 2008, pp. 244-245.102

簡易檢索 / 詳目顯示

相關論文