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研究生: 陳臆安
Chen, Yi-An
論文名稱: 利用電荷分享對基板偏壓的方法以最佳化效能和待機功耗
A Charge-Sharing Body Biasing Method for Performance and Standby Power Optimization
指導教授: 張彌彰
Chang, Mi-Chang
口試委員: 郭治群
Guo, Jyh-Chyurn
張克正
Chang, Keh-Jeng
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 70
中文關鍵詞: 次臨界區電荷分享基板效應基板偏壓最佳化
外文關鍵詞: Body Effect, VTMOS, Triple-well
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  • 中文摘要
    降低電壓是一個減少功耗非常有效的方法。然而,使用這個方法的其中一個壞處就是降低電路效能。在本篇論文裡,我們研究了多種不同的在次臨界區應用的低功耗電路和提出了一個基板偏壓插座電路以最佳化電路效能以及待機功耗。在可變動臨界電壓的金氧半電路裡可以藉由一個外部電路提供一個適當的基板偏壓,但是這也消耗了更多的功耗在對基板電容充放電。

    使用基板偏壓插座的電路利用電荷分享的方法,使PMOS的基板電容對NMOS的基板電容充電來對基板偏壓,而不需使用外部的偏壓電路。它不必使用外部的偏壓電路來對基板電容充電,因此可以節省功耗。

    當這個電路開啟時,NMOS和PMOS電晶體的基板電容將會分享它們的電荷,使得電晶體的效能提昇。以一個4位元的漣波進位家法器而言,我們發現它的效能比起一般CMOS電路可以提昇約26%。當插座關閉時,待機功耗只有比一般CMOS電路增加約2.3%。反觀,動態臨界電壓金氧半電路有較低的速度以及比起一般CMOS電路約增加500倍的待機功耗。此外,使用基板偏壓插座的方法有著較低的面積增加量。

    在這篇論文裡,由於要取得更精準的效能以及待機功耗的估計,在N井區及P井區間的寄生電容電阻也需要小心的建造模型。我們相信增加這些模型,可以使得比較更有意義。


    Voltage scaling has been shown to be an effective method to reduce power consumption. However, one of the penalties of this method is the reduction of circuit performance. In this thesis, we study various low power circuits operating in sub-threshold region and propose a body biasing socket circuit for performance and standby power optimization. The VTMOS circuit can give a proper body bias to the circuit with an external circuit, but it consumes more power to charge and discharge the body capacitance. Without the external biasing circuit, the circuit with body biasing socket uses the body sharing method to charge the NMOS body capacitance with PMOS body capacitance. It doesn’t bias the circuit by charging the body capacitance with external circuit and can save the power. This circuit, when turns on, shares the body charges of the NMOS and PMOS transistors and thus improves the transistor performance. For a simple 4-bit Ripple Carry Adder, we find the performance improved 26% as compared to the standard CMOS circuit. When the socket is turned off, the standby power is only 2.3% larger than the standard CMOS adder. In contrast the DTMOS (Dynamic Threshold MOS transistor) circuit has lower speed and with 500X larger standby power compared to the standard CMOS circuit. In addition, the area increases with the adder circuit is also much smaller with the body biasing socket method.
    In this thesis, in order to get accurate performance and standby power estimation, the transistor body terminals and the N-well, P-well parasitics are also carefully modeled. We believe with these added models, the comparisons are more meaningful.

    Content CONTENT II LIST OF FIGURES V LIST OF TABLES VIII 中文摘要 IX ABSTRACT X CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 ORGANIZATION OF THIS THESIS 2 CHAPTER 2 LOW POWER DESIGN 4 2.1 VOLTAGE SCALING 4 2.1.1 Power Dissipation 4 2.1.2 Body Effect 7 2.2 SUB-THRESHOLD LOGICS FOR LOW POWER OPERATION 11 2.2.1 Dynamic Threshold Voltage MOSFET (DTMOS) 12 2.2.2 Variable Threshold Voltage CMOS (VTCMOS) 15 2.2.3 Super Cut-Off CMOS (SCCMOS) and Multi-Threshold Voltages CMOS (MTCMOS) 16 2.3 SUMMARY 20 CHAPTER 3 NOVEL LOW POWER DESIGN AND BODY BIASING SOCKET 21 3.1 ACCURATE MODELING AND SIMULATION 21 3.1.1 Triple-well Structure 21 3.1.2 1-D Resistance Model 23 3.1.3 2-D Resistive Mesh 25 3.2 NOVEL LOW-POWER DESIGNS 26 3.2.1 DTMOS Logic Circuit 27 3.2.2 DTMOS with Current Limiter Logic Circuit 28 3.2.3 DTMOS with Subsidiary Logic Circuit 30 3.3 BODY BIASING SOCKET 31 3.3.1 Design Concepts 32 3.3.2 Architecture 32 3.3.3 Circuit Operation 33 3.3.4 Control Circuit 34 3.3.5 Body Biasing Reset Circuit 35 3.4 SUMMARY 36 CHAPTER 4 ANALYSIS OF THE BODY BIASING SOCKET 37 4.1 OPERATION 37 4.2 SIZE AND NUMBER OF TRANSISTORS 40 4.3 PERFORMANCE AND ENERGY 50 4.4 VOLTAGE DIVIDER 53 4.5 SUMMARY 56 CHAPTER 5 SIMULATION RESULTS AND COMPARISON 57 5.1 REFERENCE CIRCUIT AND PARAMETERS 57 5.2 COMPARISON 59 5.2.1 Input Capacitance of Each Gate 59 5.2.2 Delay Time 59 5.2.3 Power-Delay Product 61 5.2.4 Standby Power 62 5.2.5 Area 64 CHAPTER 6 CONCLUSION AND FUTURE WORK 67 6.1 CONCLUSION 67 6.2 FUTURE WORK 68 REFERENCE 69

    Reference
    [1] M. Meijer and J. P. Gyvez, "Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning Adaptive Techniques for Dynamic Processor Optimization," A. Wang and S. Naffziger, Eds., ed: Springer US, 2008, pp. 25-47.
    [2] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and D. Vivek, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in ISSCC 2002, IEEE International Solid-State Circuits Conference, 2002. Digest of Technical Papers. , 2002, pp. 422-478 vol.1.
    [3] M. Meijer, J. P. de Gyvez, B. Kup, B. van Uden, P. Bastiaansen, M. Lammers, and M. Vertregt, "A forward body bias generator for digital CMOS circuits with supply voltage scaling," in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2482-2485.
    [4] M. Miyazaki, G. Ono, and K. Ishibashi, "A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias," IEEE Journal of Solid-State Circuits, vol. 37, pp. 210-217, 2002.
    [5] S. Amarchinta, H. Kanitkar, and D. Kudithipudi, "Robust and high performance subthreshold standard cell design," in 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009. MWSCAS '09., 2009, pp. 1183-1186.
    [6] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and H. Chenming, "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI," IEEE Transactions on Electron Devices, vol. 44, pp. 414-422, 1997.
    [7] D. Q. F. D'Agostino, "Short Channel Effects in MOSFETs," 2000.
    [8] T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," in 42nd ISSCC., 1996 IEEE International Solid-State Circuits Conference, 1996. Digest of Technical Papers., 1996, pp. 166-167, 437.
    [9] H. Soeleman, K. Roy, and B. C. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, pp. 90-99, 2001.
    [10] H. Kawaguchi, K. Nose, and T. Sakurai, "A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1498-1501, 2000.
    [11] K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Managing subthreshold leakage in charge-based analog circuits with low-V<sub>TH</sub> transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)," IEEE Journal of Solid-State Circuits, vol. 41, pp. 859-867, 2006.
    [12] M. Kyeong-Sik, C. Hun-Dae, H. Y. Choi, H. Kawaguchi, and T. Sakurai, "Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 430-435, 2006.
    [13] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, pp. 847-854, 1995.
    [14] Z. Xin, C. Yici, Z. Qiang, and H. Xianlong, "A novel low-power physical design methodology for MTCMOS," in 2006 IEEE International Symposium on Circuits and Systems, 2006. ISCAS 2006. Proceedings., 2006, p. 4 pp.
    [15] S. Voldman, E. Gebreselasic, M. Zierak, D. Hershberger, D. Collins, N. Feilchenfeld, S. St. Onge, and J. Dunn, "Latchup in merged triple well structure," in 43rd Annual. 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings., 2005, pp. 129-136.
    [16] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and H. Chenming, "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," in International Electron Devices Meeting, 1994. IEDM '94. Technical Digest., 1994, pp. 809-812.

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