在最近的這幾年裡，由於無線產品所帶來的便利性逐漸受到重視，於是被廣泛地應用在各種不同的場合裡，如此的大量需求也造就了無線領域的蓬勃發展；同時，為了更進一步地降低無線產品的功率和價格，使得互補式金氧半導體(CMOS)成為了達成這項任務的最有潛力候選方案之一。
在一個整合的收發機裡，頻率合成器是一個很重要的建構方塊；因為在無線通訊的應用之下，頻率合成器必須具有高頻率、小的頻率間隔和高頻譜純淨度的要求。在過去的幾十年裡，要達成如此的艱難工作，最常見到的解決方案是使用三角積分器的分數型鎖相迴路，來合成出所需要的頻率。在本篇論文裡，主要採用並實現了「以直接數位方式為基礎的鎖相迴路」(DDS based PLL)，並且希望應用在DCS1800接收端上。在這個架構裡面，同時保有了直接數位頻率合成器(DDS)和傳統鎖相迴路(PLL)的優點，除此之外，還解開了在傳統鎖相迴路裡頻率間隔和穩定時間的兩難。
本篇論文所設計的頻率合成器包含了:壓控震盪源(VCO)、頻率除法器(frequency divider)、單邊頻帶混頻器(SSB mixer)、相位頻率偵測器(PFD)和電荷泵(Charge pump)，而直接數位頻率合成器和迴路率波器(loop filter)則是採用外接的方式。此篇論文大致上可以分為三個部分，第一個部分為系統階層的分析，包含了頻率上面的分配和整個合成器裡面每個建構區塊所貢獻的雜訊特性；第二個部分則為電路設計的部分，壓控震盪源和其他建構區塊也會在此作更深入的分析；最後則是晶片的實作和量測；本次晶片所使用的製程為UMC .18 μm，整個晶片的面積為1.18mm×1.05mm。

In the recent years, wireless product has been wildly used in many applications owing to the convenience for users. Such great desire also makes enormous progress in this field. In order to lower the cost and power, CMOS monolithic transceiver is the most potential candidates for achieving this tough work.

Frequency synthesizer is one of the most important building blocks in an integrating transceiver. In the past decades, delta-sigma fractional-N phase locked loop is the most widely used structure for solving the tough task of high frequency, small channel spacing and high spectrum purity which must be faced for synthesizer used in wireless application. In this project, a “DDS based syntheiszer” is proposed and implemented in UMC .18 um. This structure maintains both the advantages of direct digital synthesis (DDS) and integer-N PLL, besides it also gets rid of trade-off between channel spacing and settling time in conventional PLL.

In this project, the chip of this synthesizer contains a monolithic VCO, dividers, single sideband mixer, phase frequency detector and charge pump. The DDS and loop filter are provided externally. This thesis can be mainly divided into three parts; the first part is the system level analysis, which includes frequency plan and noise properties of the blocks in synthesizer. The second part is about circuits design. VCO will be discussed in details and other building block will also be considered. The chip implementation and measurement will be shown in the last part. This chip is implemented in UMC .18um. The chip size is 1.18mm X 1.05 mm.

[1] D. B. Leeson, ¡§A simple model of feedback oscillator noises spectrum,¡¨ in Proc. IEEE,vol. 54, pp. 136¡V154, Feb. 1966.
[2] V. Manassewitch, Frequency synthesizer theory and design. Scholars, 1980.
[3] V. F. Kroupa, Direct digital frequency synthesizers. IEEE Press, 1999.
[4] B. Razavi, Design of analog CMOS integrated circuits. McGraw Hill, 1995.
[5] N. J. R. King, ¡§Phase locked loop variable frequency synthesizer.¡¨ U.S. Patent No. 4204174.
[6] W. S. T. Yan and H. C. Luong, ¡§A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receiver,¡¨ IEEE J. Solid-State Circuits, vol. 36, pp. 204¡V216, Feb. 2001.
[7] T. Kan, L. G.C.T, and L. H.C, ¡§A 2-V 1.8-GHz fully integrated CMOS dual-loop frequency synthesizer,¡¨ IEEE J. Solid-State Circuits, vol. 37, pp. 1012¡V1020, Aug. 2002.
[8] A. Bonfanti, F. Amorosa, C. Samori, and A. L. Lacaita, ¡§A DDS-based PLL for 2.4-GHz frquency synthesis,¡¨ IEEE Trans. Circuits Syst. II, vol. 50, pp. 1007¡V1010, Dec. 2003.
[9] A. Hajimire and T. H. Lee, ¡§Design issues in CMOS differential LC oscillators,¡¨ IEEE J. Solid-State Circuits, vol. 34, pp. 717¡V724, May 1999.
[10] D. Ham and A. Hajimiri, ¡§Concept and method in optimization of integrated LC VCOs,¡¨ IEEE J. Solid-State Circuits, vol. 36, pp. 717¡V724, June 2001.
[11] H. Hayashi, M. Muraguchi, Y. Umeda, and T. Enoki, ¡§A high-Q broad-band active inductor and its application to low loss analog phase shifter,¡¨ IEEE Trans. Microwave Theory Tech.,vol. 44, pp. 2369¡V2374, Dec. 1996.
[12] M. Danesh and J. R. Long, ¡§Differentially driven symmetric microstrip inductor,¡¨ IEEE Trans. Microwave Theory Tech., vol. 50, pp. 332¡V341, Jan. 2002.
[13] B. D. Muer, M. Borremans, M. steyaert, and G. L. Puma, ¡§A 2-GHz low-phase-noise integrated LC VCO set with flicker-noise upconversion minimization,¡¨ IEEE J. Solid-State Circuits, vol. 35, pp. 1031¡V1038, July 2000.
[14] J. Craninckx and M. S. J. steyaert, ¡§A 1.8-GHz low phase noise CMOS VCO using optimized hollow spiral inductors.,¡¨ IEEE J. Solid-State Circuits, pp. 736¡V744, 1997.
[15] Y. K. Koutsoyannopoulos and Y. Papananos, ¡§Systems analysis and modeling of integrated inductors and transformers in RF IC design,¡¨ IEEE Trans. Circuits Syst., pp. 699¡V713, 2000.
[16] C. P. Yue and S. S. Wong, ¡§On-chip spiral inductors with patterned ground shields for Sibased RF IC¡¦s,¡¨ IEEE J. Solid-State Circuits, pp. 734¡V752, 1998.
[17] J. Gil and H. Shin, ¡§A simple wide-band on-chip inductor model for silicon-based RF ICs,¡¨ IEEE Trans. Microwave Theory Tech., vol. 51, pp. 2023¡V2028, Sept. 2003.
[18] D. F. Peterson, ¡§Varactor peoperties for wide-band linear-tuning microwave VCOs,¡¨ IEEE Trans. Microwave Theory Tech., vol. 28, pp. 110¡V119, Feb. 1980.
[19] N. Fong, J. O. Plouchart, N. Zamdmer, D. Lie, L.Wanger, C. Plett, and G. Tarr, ¡§A 1V 3.8-5.7GHz wide-band VCO with differentially tuned accumulation MOS SOI technology,¡¨ IEEE Trans. Microwave Theory Tech., vol. 51, pp. 1952¡V1959, Aug. 2003.
[20] E. Hegazi and A. A. Abidi, ¡§varactor characteristics, oscillator tuning curvea and AM-FM conversion,¡¨ IEEE J. Solid-State Circuits, vol. 38, pp. 1033¡V1039, June 2003.
[21] T. P. Tsividis, Operation and modeling of the MOS transistor. McGraw Hill, 1987.
[22] A.-S. Porret, T. Melly, C. C. Enz, and E. A. Vittoz, ¡§Design of higher-Q varactor for low power wireless application using a standard CMOS process,¡¨ IEEE J. Solid-State Circuits, vol. 35, pp. 337¡V345, Mar. 2000.
[23] T.-H. Lin and W. J. Kaise, ¡§A 900-MHz 2.5-mA CMOS frequency synthesizer with a automatic SC tuning loop,¡¨ IEEE J. Solid-State Circuits, vol. 36, pp. 424¡V431, Mar. 2001.
[24] S. Levantino, C. Samori, A. Bonfanti, sander L. J. Gierkink, A. L. Lacaita, and V. Boccuzzi, ¡§Frequency dependence on bias current in 5-ghz CMOS VCOs: impact on tuning range and flicker noise upconversion,¡¨ IEEE J. Solid-State Circuits, vol. 37, pp. 1003¡V1011, Aug 2002.
[25] A. kral F. Behbahani and A. A. Abidi, ¡§RF-CMOS with switched tuning,¡¨ in Constom IC Conf., pp. 555¡V558, May 1998.
[26] T. A. Papalias, T. T. Lee, A. Hajimiri, R. W. Dutton, and T. H. Lee, ¡§Reprogrammable, wide tuning rang 1.6Ghz CMOS VCO with low phase noise variation,¡¨ in Proc of IEEE.international Symposium on Radio Frequency Integrated Circuits, pp. 479¡V482, 2004.
[27] N. H. W. Fong, J.-O. Plouchar, N. Zamdmer, D. Lie, L. F. Wagner, C. Plett, and N. G. Tarr, ¡§Design of wide-band CMOS VCO for multiband wireless LAN applicaitons,¡¨ IEEE J. Solid-State Circuits, vol. 38, pp. 1333¡V1342, Aug. 2003.
[28] M. Terrovities, M. Mack, K. Signh, and M. Zargari, ¡§A 3.2 to 4 GHz, 0.25um CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN,¡¨ in IEEE Int. Solid-State Circuits Conf.Digest of Technical Papers (ISSCC), Feb. 2004.
[29] Z. L. K. O, ¡§A 900-MHz 1.5V CMOS voltage- contrled oscillator using switched resonators with a wide tuning range,¡¨ IEEE Microwave Wireless Compon. Lett., vol. 13, pp. 137¡V139, Apr. 2003.
[30] J. J. Rael and A. A. Abidi, ¡§Physical processes of phase noise in differential LC oscillators,¡¨in Proc. IEEE Custom Integrated Circuits Conf., (Orlando), pp. 560¡V572, 2000.
[31] E. Hegazi, H. Sj¡Loland, and A. A. Abidi, ¡§A iltering technique to lower LC oscillator phase noise,¡¨ IEEE J. Solid-State Circuits, vol. 36, pp. 1921¡V1930, Dec. 2001.
[32] P. Andreani and H. sj¡Loland, ¡§Tail current noise suppression in RF CMOS VCO,¡¨ IEEE J.Solid-State Circuits, vol. 37, pp. 342¡V348, Mar. 2002.
[33] H. O. Johansson, ¡§A simple precharged CMOS phase frequency detector,¡¨ IEEE J. Solid-State Circuits, vol. 33, pp. 250¡V299, Feb. 1998.