Performance and Power Optimization for Power Gating Designs

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研究生：	仇德軒 Chiou, De-Shiuan
論文名稱：	Performance and Power Optimization for Power Gating Designs 針對功率閘控制設計之效能及功率最佳化
指導教授：	張世杰 Chang, Shih-Chieh
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2009
畢業學年度：	98
語文別：	英文
論文頁數：	74
中文關鍵詞：	功率閘、漏電功率、睡眠電晶體網路
外文關鍵詞：	power gating, leakage power, DSTN
相關次數：	點閱：2 下載：0
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功率閘控已經成為降低漏電功率的最有效的方法之一。早先被提出的分散式睡眠電晶體網路(Distributed Sleep Transistor Network, DSTN)，藉由串接虛擬接地線來最小化流過睡眠電晶體的瞬時最大電流(Maximum Instantaneous Current, MIC)。在這篇論文裡，我們提出了決定睡眠電晶體大小的方法來最小化漏電功率。
首先，我們提出了一個時間複雜度為O(nlgn)的演算法，來有效估計睡眠電晶體兩端的壓降的上限值。我們的方法並考慮到不同邏輯叢集間放電電流的關連性，藉此避免了過份悲觀的壓降估計。第二，我們把單一一個時脈週期細分為多個時間單元，來觀察瞬時最大電流、壓降、和睡眠電晶體網路三者間的關連性。藉由這層關係，我們針對DSTN架構，提出了縮小睡眠電晶體總面積的演算法。有鑑於在功率閘設計中，常會加上去耦合電容來減少壓降等雜訊，因此我們決定睡眠電晶體大小的方法同時也考慮到了去耦合電容的效應。而針對我們方法的收斂性，我也提出了嚴謹的證明。

Power gating is one of the most effective ways to reduce leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area for power gating by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current flowing through sleep transistors. In this thesis, we propose two sleep transistor sizing methodologies for leakage power minimization. First, we present an O(n lg n)-time algorithm for efficiently estimating a tight upper bound of the voltage drop across sleep transistors in DSTN structure. Our algorithm takes the correlation between discharge current of different logic clusters into consideration, which avoids over-pessimistic voltage drop estimation. Secondly, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in DSTN designs. In our sizing method, the effect of decoupling capacitances is also taken into account since decaps are commonly inserted in a power gating design to reduce the IR drop noise. Also, the convergence of our sizing algorithm is guaranteed through the theorem we proposed.

Content
Abstract    2
Content    3
List of Figures    5
List of Tables    7
Chapter 1    Introduction    8
1.1    Leakage Power Challenge    8
1.2    Organization    10
1.2.1 Sleep Transistor Sizing Considering Charge Balancing    10
1.2.2 Sleep Transistor Sizing Considering Temporal Correlation    13
Chapter 2    Sleep Transistor Sizing Considering Charge Balancing    17
2.1    Relation between Voltage Drop and Timing Performance    17
2.2    Sleep Transistor Sizing Mechanism    18
2.3    Fast and Accurate Voltage Drop Estimation    20
2.3.1 Modeling of the DSTN Structure    20
2.3.2 Calculate IST Using Discharging Matrix    20
2.3.3 General Form of Discharging Matrix    21
2.3.4 Calculations of Discharging Matrix Ψ    22
2.3.5 Problem Formulation    24
2.3.6 Fast and Accurate MIC(STi) Estimation    27
2.4    Numerical Example of the Constrained LP Problem    29
2.5    Proof of Theorem 1    30
2.6    Sleep Transistor Sizing for the DSTN Structure    35
2.7    Proof of Theorem 2    37
2.8    Experimental Results    40
2.9    Summary    41
Chapter 3    Sleep Transistor Sizing Considering Temporal Correlation    42
3.1    Physical Implementation of DSTN    42
3.2    Relation between Size and MIC of a Sleep Transistor    44
3.3    Resistor Network Modeling of DSTN    45
3.4    Discharging Matrix Ψ    47
3.5    MIC Estimation Using Time-Frame Partitioning    49
3.6    Variable-Length Time-Frame Partitioning    52
3.7    Considering Decoupling Capacitance    56
3.8    Problem Formulation of Sleep Transistor Sizing    59
3.9    Sleep Transistor Sizing Algorithm    60
3.10    Experimental Results    65
3.11    Summary    69
Chapter 4    Conclusion    70
References    71



List of Figures
Figure 1 1: Leakage power of a single inverter increases exponentially with technology scaling. (from [6])    8
Figure 1 2: Illustration of MTCMOS circuit scheme..    10
Figure 1 3(a): Cluster-based: each cluster is connected to one sleep transistor.    11
Figure 1 3(b): DSTN: all the virtual grounds are connected together..    11
Figure 1 4: Power gating scheme..    13
Figure 1 5: The MIC waveforms of two clusters..    15
Figure 2 1: Resistance network modeling for DSTN..    20
Figure 2 2: A resistance network of a DSTN design with n = 3..    22
Figure 2 3(a): From node 1 to node 2    23
Figure 2 3(b): From node 3 to node 2    23
Figure 2 3(c): From C2 to node 2    24
Figure 2 4: Different combinations of clusters’ MIC information    26
Figure 2 5: A Linear Programming problem to estimate MIC(ST3)    26
Figure 2 6: A balanced full binary tree to depict the correlation-constraints insertion rule for the design with 4 clusters    27
Figure 2 7: The exact algorithm solving the maximization problem under MIC constraints    28
Figure 2 8: A numerical example of MIC(STi) estimation    29
Figure 2 9: The constraint tree for the CTM problem in Figure 2-8    31
Figure 2 10: Another example with two unsaturated path A→B2→C3 and A→B2→C4    32
Figure 2 11: Subtract ICw and add ICs by q will improve the solution    33
Figure 2 12: Sleep transistor sizing algorithm    36
Figure 2 13(a): A general conductance network for STj and CSi    38
Figure 2 13(b): A general conductance network for CSi    38
Figure 3 1(a): A DSTN implementation scheme. The gates in the same row after placement are grouped into a cluster. Power gating cells are inserted on both sides of each row    43
Figure 3 1(b): Layout of a power gating design    43
Figure 3 2: Resistor Network modeling of a DSTN structure    45
Figure 3 3: Discharging current in a resistor network modeling    45
Figure 3 4: MIC(Ci) waveforms of AES    49
Figure 3 5: EMIC(STi,Tj) waveforms    51
Figure 3 6: MIC(Ci,Tj) waveforms of different partitions    54
Figure 3 7: Variable length n-way partitioning algorithm    55
Figure 3 8: Resistor and Capacitor network modeling for DSTN    56
Figure 3 9: Sleep transistor sizing problem formulation    59
Figure 3 10: Sleep transistor sizing algorithm    61
Figure 3 11: Step-by-step illustration of a complete iteration of our algorithm    63
Figure 3 12: MIC information of clusters in each time frame as input    64
Figure 3 13: EMIC(STi,Tj) and Slack(STi,Tj) in the second iteration    64
Figure 3 14: The implementation flow of sleep transistor sizing for DSTN    66
Figure 3 15: Sleep transistors in AES    69


List of Tables
Table 2 1: Total Sleep Transistor Area    40
Table 3 1: Comparisons of Total Sleep Transistor Area and Runtime    67
Table 3 2: Maximum Instantaneous Current through Sleep Transistors    68

                                

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