低溫複晶矽薄膜電晶體由於廣泛的應用在主動陣列液晶顯示器(AMLCD)和有機發光二極體而受到高度的矚目，且其不僅能當作一般的陣列開關，亦能應用於如靜態隨機存取記憶體(SRAM)，影像感應器(Linear image sensor)和非揮發性記憶體等。此外，由於電路的集積度不斷的增加，系統整合在面板上是未來的的趨勢，即將週邊電路，關鍵元件，驅動電路等整合在玻璃基板上。低溫複晶矽更是其關鍵技術。而非揮發性記憶體已經發展三十年餘，其在半導體工業中所扮演的角色也愈來愈重要。在本論文的第一部分提出具三向閘極奈米線結構雙複晶矽薄膜電晶體非揮發性記憶體，實驗果指出，具三向閘極奈米線結構的元件比單通道結構的元件有更優越的電性，由於奈米線結構有較多的轉角數目，其三向閘極的額外轉角電場使元件有更好的閘極控制能力，增加了元件的寫入及抹除效率。此外，本論文亦製作了不同閘極長度及不同耦合比的元件，探討在不同尺寸及不同耦合比的元件在電性上的影響。研究指出複晶矽的晶粒邊界缺陷對於薄膜電晶體的電性會有劇烈的影響，因此降低晶粒邊界缺陷可以改善薄膜電晶體的特性。在本論文的第二部分提出具氨電漿保護的雙複晶矽薄膜電晶體非揮發性記憶體，氨電漿保護可以降低晶粒邊界的陷井狀態密度，提升元件性能，可增加記憶窗口(memory window)，降低操作電壓，減少寫入抹除時間，並提高儲存時間。

In recent years, low-temperature polycrystalline silicon thin-film transistors (poly-Si TFTs) have drawn much attention because of their widely applications on active matrix liquid crystal displays (AMLCDs) , and organic light-emitting diodes (OLEDs) . Furthermore, low-temperature poly-Si TFTs will help to carry out the three-dimensional integrated circuits (3D-ICs) or multilayer Si ICs for system-on-chip (SoC) applications and fully functional system-on-panels (SoPs) in the future.It means that periphery circuits, key devices, and driving circuits all integrated on glass substrate. And nonvolatile memory (NVM) have been manufactured over thirty years, it has been becoming more and more important in the semiconductor industry because of their widely application for data storage. Based on previous experimental results, the NWs poly-Si TFT has the superior electrical characteristics due to the tri-gate structure and additional corner current induced by corner effect. In first part of this thesis proposed the twin poly-Si thin film transistor nonvolatile memory with tri-gate nanowires (NWs) structure. The experimental results show that the NWs device has superior electrical characteristic than the single channel (SC) one. Since the crowding of the gate fringing field at the narrow channel surface of NWs causes the large electrical field, the NWs devices with have the better gate control ability. The high electrical field verified enhancement of P/E efficiency in twin poly-Si TFT NVM due to the corner effect. Besides, this thesis demonstrated the different gate length and different coupling ration devices to discuss the coupling ration effect and floating gate length effect.
The presence of polysilicon grain boundary defects in the channel region of TFTs drastically affects the electrical characteristics. Reducing the number of polysilicon grain boundary defects will improve the performance of poly-Si TFTs. NH3 plasma passivation has been reported to reduce the number of trap–states in poly-Si grain boundaries, yielding high-performance poly-Si TFTs. Thus, in the second part of this thesis, the twin poly-Si TFT NVM with NH3 plasma passivation is demonstrated. NH3 plasma passivation present better electrical characteristic, increase memory window, improve retention and decrease operation voltage.

Reference
[1-1] Wegener H.A.R. et al. “The variable threshold transistor, a newly electrically alterable nondestructive read-only storage device“ . IEDM TECH. Dig. 1967
[1-2] Paolo Cappelletti, Carla Golla, Piero Olivo and Enrico Zanoni ”Flash memory”
[1-3] Kahng D. and Sze S.M. “A floating gate and its application to memory devices”. Bell syst. Tech. J.,46, p. 1288, 1967
[1-4]Frohman-Bentchkowsky D. “A fully decoded 2084-bit electrically programmable
MOS-ROM”. IEEE ISSCC TECH. Dig., p.80, 1971
[1-5] Harari E., Schmitz L.,Troutman B. And Wang S. “A 256 bit nonvolatile static RAM“. IEEEE ISSCC Tech. Dig., p.108, 1978
[1-6] Kynett V.N., Baker A., Fandrich M., Hoekstra G., Jungroth O., Kreifels J. And Wells S. “An in-system reprogrammable 256K CMOS Flash memory“, ISSCC Tec. Dig., p.132, 1988
[1-7] A. T. Wu, T. Y. Chan, P. K. Ko,and C. Hu, ”A novel high-speed,5V programming EPROM structure with source-side-injection”, IEDM Tech. Dig, pp.584-587,1986
[1-8] M. Cao, T. Zhao, K. C. Saraswat, and J. D. Plummer, “A Simple EEPROM Cell Using Twin Polysilicon Thin Film Transistors”, IEEE Electron Device Lett., vol. 15, p. 304-306, Aug. 1994.
[1-9] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The Fabrication and Characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process”, IEEE Trans. Electron Devices, vol. 43, p. 1930-1936, Nov. 1996.
[1-10]J. W. Lee, N. I. Lee, H. J. Chung, and C. H. Han, “Improved Stability of Polysilicon Thin-Film Transistors under Self-Heating and High Endurance EEPROM Cells for Systems-On-Panel”, in IEDM Tech. Dig., p. 265 – 268, 1998.
[1-11]Anish Kumar K.P. and J. K. O. Sin, “A Simple Polysilicon TFT Technology for Display Systems on Glass”, in IEDM Tech. Dig., p. 515 – 518, 1997.
[1-12]A. J. Walker, S. Nallamothu, E. H. Chen, M. Mahajani, S. B. Herner, M. Clark, J. M. Cleeves, S.V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications”, in VLSI Tech. Dig., 29, p. 29 – 30, 2003.
[1-13]E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory” in IEDM Tech. Dig., , 2006.
[1-14] Y. C. Wu, C. Y. Chang, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H Tai, and S. M. Sze, “High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels” in IEDM Tech. Dig., p. 777 – 780, 2004.
[1-15] T. Unagami, and O. Kogure, IEEE Trans. Electron Devices, 35, 1986, (1988).
[1-16] Y. C. Wu, T. C. Chang, C. Y. Chang, C. S. Chen, C. H. Tu, P. T. Liu, H. W. Zan, and Y. H. Tai, Appl. Phys. Lett., 84, 3822, (2004).
[1-17] H. C. Cheng, F. S. Wang, and C. Y. Huang, IEEE Trans. Electron Devices, 44, 64, (1997).
[1-18] C. H. Seager and D. S. Ginley: Appl, Phys. Lett. 34 (1979) 337.
[1-19] D. R. Campbell: Appl. Phys. Lett. 39 (1980) 604.
[1-20] M. J. Tsai, F. S. Wang, K. L. Cheng, S. Y. Wang, M. S. Feng and H. C. Cheng: Solid State Electron. 38 (1995) 1233.
[1-21] F. S. Wang, M. J. Tsai, and H. C. Cheng: IEEE Electron Device Lett. 16 (1995) 503
[2-1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells: an overview,”
Proceedings of The IEEE, 85, 1248-1271,1997
[2-2] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, p.59.
[2-3] J. Moll, Physics of Semiconductors. New York: McGraw-Hill, (1964)
[2-4] M. Lezlinger and E. H. Snow, J. Appl. Phys., 40, 278 (1969)
[2-5] Christer Sevensson and Ingemar Lundstrom, J. Appl. Phys., 44, 4657 (1973)
[2-6] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. Solid-State Circuits, 14, 442 (1979)
[2-7] K. Hasnat, C.-F. Yeap, S. Jallepalli, W.-K. Shin, S. A. Hareland, V.M. Agostinelli, A. F. Tasch and C. M. Maziar, “A Pseudo-Lucky electron model for simulation of electron fate current in submicron NMOSFET’s”, IEEE TRANSACTION on Electron Devices, VOL.43, NO.8, pp.1264~pp.1273, August 1996
[2-8] Souvik Mahapatra, S. Shukuri and Jeff Bude, “CHISEL Flash EEPROM-Part I: Performance and Scaling”, IEEE TRANSACTION on Electron Devices, VOL.49, NO.7, pp.1296~pp.1301, July 2002
[2-9] David Esseni, Luca Selmi, Andrea Ghetti and Enrico Sangiorgi, “The Scaling Properties of CHISEL and CHE Injection Efficiency in MOSFETs and Flash Memory Cells”, IEEE IEDM pp.275~pp.278, 1999
[2-10] Luca Selmi and David Esseni, “A Better Understanding of Substrate Enhanced Gate Current in VLSI MOSFET’s and Flash Cells-Part II: Physical Analysis”, IEEE TRANSACTION on 84 Electron Devices, VOL.46, NO.2, pp.376~pp.381, February 1999
[2-11] F. Matsuoka, H. Hayashida, K. Hama*, Y. Toyoshima, H. Iwai, and K. Maeguchi “DRAIN AVALANCHE HOT HOLE INJECTION MODE ON PMOSFETs” IEDM Tech. Dig, pp.18-21,1988
[2-12] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash
Memory,” Proceedings of the IEEE., 91, 489-502 (2003)
[2-13]C. Papadas, G. Ghibaudo, G. Pananakakis, C. Riva, P. Ghezzi, C. Gounelle, and P. Mortini, “Retention characteristics of single-poly EEPROM cells,” in Proc. European Symp. Reliability of Electronic Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, Oct. 7–10, 1991, pp. 517–522.
[2-14] A. Watts, “Built-in reliability for 10 FITS performance on EPROM and Flash memory,” SGS-Thomson Microelectronic, Agrate Brianza, Italy, Tech. Art. TA 109, Nov. 1991.
[2-15] N. R. Mielke, “New EPROM data loss mechanisms,” in Proc. IRPS, 1983, pp. 106–113.
[2-16] S. Aritome, R. Shirota, G. Hemnik, T. Endoh, and F. Masuoka, “Reliability issues of Flash memory cells,” Proc. IEEE, vol. 81, pp. 776–788, May 1993.
[2-17] N. R. Mielke, “New EPROM data loss mechanisms,” in Proc. IRPS, 1983, pp. 106–113.
[2-18] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, “Failure mechanisms of flash cell in program/erase cycling,” IEDM Tech. Dig., p.291 (1994)
[3-1] S. Tam, P. K. Ko, and C. Hu, “ Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s” IEEE Trans. Electron Devices, vol. 31, p. 1116-1125, Sep. 1984.
[3-2] S. C. Chen, T. C. Chang, P. T Liu, Y. C. Wu, P. S. Lin, B. H. Tseng, J. H. Shy, S. M. Sze, C. Y. Chang, and C. H. Lien, “ A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory”, IEEE Electron Device Lett., vol. 28, p. 809-811, Sep. 2007.