資料路徑通常是影響晶片效能的重要部分。本篇論文會以資料路徑的規則性質與 bit-slice 結構性質，去簡化得到佈局圖的過程與把晶片效能及面積最佳化。現今的高效能資料路徑設計，通常還需要手動的方式設計，設計者會識別和利用資料路徑的規則性質，來取得好的效能，不過這使得設計時間拉長且不能平順的整合到自動化擺置與繞線設計流程。傳統擺置工具把資料路徑電路視為隨機的邏輯電路，使得佈局圖的效能不是最佳化的。對於資料路徑的擺置與繞線，必須考慮到規則特性，這會使得連接線縮短來增進效能，與擺置緊密讓晶片面積縮小。在這篇論文中，我們提出一個資料路徑的線性擺置演算法和包含路徑資訊的模型。我們保留資料路徑的規則性質以取得高密度的佈局圖。資料路徑中的區塊會被儘可能緊密的擺置，以減少連接線的長度和改善效能。我們也以計算繞線所需通道數的方式，來同時考慮繞線的擁塞程度。實驗結果顯示我們的方式對取得好的佈局結果是的有幫助的。

Datapath are usually on the critical path that determines the chip performance. We should take advantage of their regular and bit-slice structure to simplify the layout task and optimize the performance and area. Traditional placement tools do not treat datapath cells any different from random logic cell. Therefore, the layout quality is far from optimal. We propose a path model and a linear placement algorithm for datapath placement. We preserve the regularity of datapath structure for high-density layout. Blocks on the critical path are placed as tightly as possible to reduce the wire length and improve the timing. We also consider the routing congestion by carefully estimating the number of tracks needed. Experimental results are very promising.

[1] T. T. Ye, G. D. Micheli, "Data path placement with Regularity", in Proceedings IEEE/ACM International Conference on Computer Aided Design, pp. 264-270, 2000.
[2] T. Kutzschebauch, "Regularity driven logic synthesis", in Proceedings IEEE/ACM International Conference on Computer Aided Design, pp. 439-446, 2000.
[3] Y. Tsujihashi et al., "A High-Density Data-Path Generator with Stretchable Cells", in IEEE Journal of Solid-State Circuits, pp. 2-8, 1994
[4] T. Sendar, C. Sechen, "Automatic Datapath Tile Placement and Routing", in Proceedings of Design, Automation and Test in Europe, pp. 552-559, 2001.
[5] R. X. T. Nijsen, C. A. J. van Eijk, "Regularity layout generation of logically optimized datapaths", in Proceedings of International Symposium on Physical Design, pp. 42-47, 1997.
[6] S. R. Arikati, R.Varadarajan, "A signature based approach to regularity extraction", in Proceedings of International Conference on Computer Aided Design, pp. 542-545, 1997.
[7] A. Chowdhary, S. Kale, P. K. Saripella, N. K. Sehgal, R.K. Gupta, "Extraction of functional regularity in datapath circuits", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1279-1296, 1999.
[8] J. S. Yim, C.M. Kyung, "Datapath layout optimisation using genetic algorithm and simulated annealing", in Proceedings of IEE Computer Digital Technical, pp. 135-141, 1998.
[9] H. Nakao, O. Kitada, M. Hayashikoshi, K. Okazaki, Y. Tsujihashi, "A high density datapath layout generation method under path delay constraints", in Proceedings of Custom Integrated Circuit Conference, pp. 135-141, 1993.
[10] M. Munch, N. Wehn, M. Glesner, "Optimum simultaneous placement and binding for bit-slice", in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 735-740, 1995.
[11] P. Ienne, A. GrieBing, "Practical experiences with standard-cell based datapath design tools. Do we really need regular layouts?", in Proceedings of Design Automation Conference, pp. 396-401, 1998.
[12] S. W. Hur, J. Lillis, "Relaxation and Clustering in a Local Search Framework: Application to Linear Placement", in Proceedings of Design Automation Conference, pp. 360-366, 1999.
[13] J. Kim, S. M. Kang, "A Timing-driven Data Path Layout Synthesis with Integer Programming", in Proceedings of International Conference on Computer Aided Design, pp. 716-719, 1995.
[14] N. Buddi et al., "Layout Synthesis for Datapath Designs", in Proceedings of European Design Automation Conference, pp. 86-90, 1995.
[15] E. Auer, W. Schiele, G. Sigl, "A New Linear Placement Algorithm for Cell Generation", in Proceedings of International Conference on Computer Aided Design, pp. 486-489, 1991.
[16] S. Chowdhury, "Analytical Approaches to the Combinatorial Optimization in Linear Placement Problems", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 630-639, 1989.
[17] P.Kurup, T.Abbasi, "Logic Synthesis Using Synopsis", Second Edition, Kluwer Academic Publishers, 1998.
[18] Cadence Design Systems, Inc., "LEF/DEF Language Reference", Product Version5.0, February 1997.