此篇論文介紹應用於神經刺激電路的脈波產生器以及應用於神經訊號紀錄的類比數位轉換器。 此脈波產生器電可提供廣範圍的刺激輸入訊號, 有助於關於如何達到有效神經刺激的研究。 量測結果同時也顯示此電路不需消耗很大的電。
此篇論文也提出由指數與對數電路實現的類比數位轉換器。 藉由指數與對數電路的特性, 此種類比數位轉換器可減少在神經訊號紀錄時, 前端放大器的放大倍率, 因此也減低了電路得功率, 同時也可節省晶片面積, 因此可降低晶片電路製成本。

This thesis describes neural stimulation and recording circuits based on time encoding. The pulse generation circuit implemented for neural stimulation allows for programmable and flexible stimulation using a time encoding scheme. Experimental results are presented for the pulse generation circuit and demonstrate that the pulse generation circuit consumes 142μW from a 5-V supply.
An exponential-logarithmic analog-to-digital converter is designed to minimize large pre-amplification for neural signal recording. The ADC performs A/D conversion using a logarithmic-exponential model. This architecture successfully achieves area conservation and therefore promises a significant reduction in cost.

Bibliography

[1]N. A. Campbell, J. B. Reece, “Biology,” Pearson Education, 2004

[2]Fitzsimmons, N. A., Lebedev, M. A., Peikon, I. D., 3 and Nicolelis, M. A., “Extracting Kinematic Parameters for Monkey Bipedal Walking from Cortical Neuronal Ensemble Activity” Frontiers in Integrative Neuroscience, March, 2000.

[3]Acharya, S., Tenore, F., Aggarwal, V., Etienne-Cummings, R., Schieber, M., Thakor, N., “Decoding Individuated Finger Movements Using Volume-Constrained Neuronal
Ensembles in the M1 Hand Area,” IEEE Transactions on Neural Systems and Rehabilitation Engineering, Vol. 16, No. 1, Feb. 2008.

[4]Ghazanfar, A. A., Stambaugh, C. R., and Nicolelis, M. A. L., “Encoding of Tactile Stimulus Location by Somatosensory Thalamocortical Ensembles,” Journal of Neuroscience, 3761–3775, May 15, 2000.

[5]Rousche, P. J., Normann, R. A., “Chronic Recording Capability of the Utah Intracortical Electrode Array in Cat Sensory Cortext,” Journal of Neuroscience Methods, 1998.

[6]Brown, E. N., Kass, R. E., and Mitra, P., “Multiple Neural Spike Train Data Analysis: State-of-the-Art and Future Challenges,” Nature, Vol. 7, No. 5, May 2004.

[7]Cardin, J. A., Carlén, M., Meletis, K., Knoblich, U., Zhang, F., Deisseroth, K., Tsai, L., Moore, C., “Targeted Optogenetic Stimulation and Recording of Neurons in vivo Using Cell-Type-Specific Expression of Channelrhodopsin-2,” Nature, Vol. 5, No. 2, 2010.
[8]Yang, Y., DeWeese, M. R., Otazu1, G. H., Zador, A. M., “Millisecond-Scale Differences in Neural Activity in Auditory Cortex Can Drive Decisions,” Nature, Oct, 2008.
[9]Hamed, S. B., Schieber, M. H., and Pouget, A.., “Decoding M1 Neurons During Multiple Finger Movements,” Journal of Neurophysiology, April 2007.

[10]Blum, R. A., Ross, J. D., Brown, E. A., DeWeerth, S. P.,"An Integrated System for Simultaneous, Multichannel Neuronal Stimulation and Recording," IEEE Transactions on Circuits and Systems, Vol. 54, No. 12, Dec. 2007.

[11]Wagenaar, D. A., Pine, J., Potter, S. M, "Effective Parameters for Stimulation of Dissociated Cultures Using Multi-Electrode Arrays," Journal of Neuroscience Methods, Vol. 138, 2004.

[12] Eversmann, B., Jenkner, M, Hofmann, F, Paulus, C., Brederlow, R., Holzapfl, B., Fromherz, P., Merz, M., Brenner, M., Schreiter, M., Gabl, R., Plehnert, K., Georgiou, M., Eckstein, J., Toumazou, C.," A 126-μW Cochlear Chip for a Totally Implantable System," IEEE Transactions of Solid-State Circuits, Vol. 40, No. 2, Feb. 2005.

[13]Sivaprakasam, S., Liu,W., Wang, G., Weiland, J. D., Humayun, M., " Architecture Tradeoffs in High-Density Microstimulators for Retinal Prosthesis," IEEE Transactions on Circuits and Systems, Vol. 52, No. 12, Dec. 2005.

[14]Yang, D. X. D., Fowler, B., Gamal, A. E., “A Nyquist-Rate Pixel-Level ADC for CMOS Image Sensors,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, March 1999.

[15]Lai, C., King, Y., S., Huang, "A 1.2-V 0.25-μm Clock Output Pixel Architecture With Wide Dynamic Range and Self-Offset Cancellation," IEEE Sensors Journal, Vol. 6, No. 2, Dec. 2006.

[16]Bermak, A, “An 8/4-bit Reconfigurable Digital Pixel Array with On-Chip Non-Uniform Quantizer," IEEE Custom Iintegrated Circuits Conference, 2005.

[17]Bermak, A, “A CMOS Imager with PFM/PWM based Analog-to-Digital Converter," IEEE International Symposium On Circuits And Systems, 2002.
[18]Eversmann, B., Jenkner, M, Hofmann, F, Paulus, C., Brederlow, R., Holzapfl, B., Fromherz, P., Merz, M., Brenner, M., Schreiter, M., Gabl, R., Plehnert, K., Steinhauster, M., Eckstein, G., Landsiedel, D., Thewes, R.,"A 128 × 128 CMOS Biosensor Array for Extracellular Recording of Neural Activity," IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, Dec. 2003.

[19]Heer, F., Hafizovic, S., Franks, W., Blau, A., Ziegler, C., Hierlemann, A., “CMOS Microelectrode Array for Bidirectional Interaction With Neuronal Networks,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 7, July. 2006.

[20]Edward, K.F. L., Lam, A., “A Matching Technique for Biphasic Stimulation Pulse," IEEE International Symposium On Circuits And Systems, 2007.

[21]Lee, T. H., Donnelly, K. S., Ho, J. T. C., Zerbe, J., Johnson, M. G., Ishikawa, T., "A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM," IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, Dec. 1994.

[22]Garlepp, B.W., Donnelly, K.S., Jun Kim; Chau, P.S., Zerbe, J.L., Huang, C., Tran, C.V., Portmann, C.L., Stark, D., Yiu-Fai Chan, Lee, T.H., Horowitz, M.A., "A Portable Digital DLL for High-Speed CMOS Interface Circuits," IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, Dec. 1999.

[23]Naraghi, S.; Courcy, M.; Flynn, M.P., “A 9b 14µW 0.06mm2 PPM ADC in 90nm Digital CMOS ,” IEEE International Symposium On Circuits And Systems, 2009.

[24]Laurent, D.G., "Sense Amplifier Signal Margins and Process Sensitivities,” IEEE Transactions on Circuits and System I: Fundamental Theory and Applications, Vol. 49, No. 3, March 2002.

[25]Chi, Y.M.; Mallik, U.; Choi, E.; Clapp, M.; Gauwenberghs, G.; Etienne-Cummings, R., “CMOS Pixel-Level ADC with Change Detection,” IEEE International Symposium On Circuits And Systems, 2006.

[26]Olsson III, R. H., Wise, K. D., “A Three-Dimensional Neural Recording Microsystem with Implantable Data Compression Circuitry,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 125, Dec. 2005.

[27]Singhal, G., Acharya, S., Davidovics, N., Jiping He, Thakor, N., “Including Planning Activity in Feature Space Distributes Activation over a Broader Neuron Population,” IEEE Engineering in Medicine and Biology Society, 2007
[28]Baker, M. W.; Sarpeshkar, R., “A Low-Power High-PSRR Current-Mode Microphone Preamplifier,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 10, Oct. 2003.
[29]Kleinfelder, S. SukHwan Lim Xinqiao Liu El Gamal, A. “A 10000 Frames/s CMOS Digital Pixel Sensor,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, Dec. 2001.
[30]Harrison, R.R. Charles, C., “A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 6, June 2003.
[31]Johns, D., Martin, K., “Analog Integrated Circuit Design,” John Wiley & Sons, Inc., 1997
[32] Razavi, B., “Desgin of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001
[33]Ringh, U., Jansson, C. and Liddiard, K. , “Readout Concept Employing a Novel on Chip 16-Bbit ADC for Smart IR Focal Plane Arrays,” in Proc. SPIE, vol. 2745, pp. 99–110, (Orlando, FL), April 1996.

[34]Pain, B. and Fossum, E., “Approaches and Analysis for on-Focal-Plane Analog-to-Digital Cconversion,” in Proc. SPIE, vol. 2226, pp. 208–218, (Orlando, FL), April 1994.

[35]Wu, C. S., “Voltage-mode and Current-mode Neural Stimulation Circuits for Carbon-Nanotube-Coupled Microelectrode Array,” Thesis, 2010

[36]Jansson, J. P., Mantyniemi, A., and Kostamovaara, J. , “A CMOS Time-to-Digital Converter with Better than 10 ps Single-Shot Precision,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 6, pp. 1286-1296, June 2006.

[37]Yang, H. Y. and Sarpeshkar, R., “A Time-Based Energy-Efficient Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 8, pp. 1590-1601, Aug. 2005.

[38]Fusayasu, T., “A Fast Integrating ADC Using Precise Time-to-Digital Conversion,” IEEE Nuclear Science Symp., pp. 302-304, Oct. 2007.

[39]E. Delagnes et al., “A Low Power Multi-Channel Single Ramp ADC with Up to 3.2 GHz Virtual Clock,” IEEE Trans. Nuclear Science, Vol. 54, No. 5, part 2, pp. 1735-1742, Oct. 2007.

[40]Yang, H. Y. and Sarpeshkar, R., A Bio-Inspired Ultra-Energy-Efficient Analog-to-Digital Converter for Biomedical Applications, IEEE Transactions on Circuits and Systems, Vol. 53, No. 11, November 2006

[41]Yin, M. and Ghovanloo, M., Using Pulse Width Modulation for Wireless Transmission of Neural Signals in Multichannel Neural Recording Systems, IEEE Transactions on Neural Systems and Rehabilitation Engineering, Vol. 17, No. 4, AUGUST 2009