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研究生: 江偉民
Wei-Min Chiang
論文名稱: 無線都會網路基頻處理器之設計與實作
Design and Implementation of a WiMAX Baseband Processor
指導教授: 馬席彬
Hsi-Pin Ma
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 95
中文關鍵詞: 無線區域網路無線都會網路正交分頻多工調變快速傅利葉轉換
外文關鍵詞: Wireless Local Access Network, Wireless Metropolitan Network, Orthogonal Frequency Division Multiplexing, Fast Fourier Transform
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  • 隨著網際網路的蓬勃發展,無線上網也變得非常流行,然而無線區域網路已經滿足不了人們的需求,因此、Worldwide Interoperability for Microwave Access 大力推廣無線都會網路(WiMAX)。IEEE 802.16-2004 為WiMAX所依據的無線都會網路標準(WMAN),主要在擬定無線都會網路實體層(PHY)與控制層(MAC)的技術與規格,其系統應用在2至66 GHz之間,為一點對多點的收發系統(PMP),調變系統為正交分頻多工,快速傅利葉轉換為256點。無線都會網路可算是無線區域網路的擴大版,它能與WLAN互補互足,以達到無線網路更高的品質。
    本論文提出一針對無線寬頻網路標準,設計與實作之基頻處理器。首先使用SystemC語言,建立起標準中所規範的發射機,無線通道模組,以及具有同步功能及還原功能的接收機。接收機的部份為本論文所著重的地方,不但要克服無線通道對訊號所造成的效應,並且需要針對不同的調變技術(發射機),還原其應得的資料。在完成系統模擬之後,利用Verilog語言進行電路設計與實現,最後並利用FPGA實驗版驗證該電路功能的正確性。
    在建構系統架構上,大多採用較簡易、低複雜度的演算法,但在效能上還能達到系統相關要求,這是為了之後在電路設計上,能夠用較小的面積消耗而完成電路設計。在電路設計上,採用不同的簡化法以及取代法,為了是能夠讓整體的電路更具有競爭力,不過這都要在能達到系統要求下所做的改進。本論文不但建立了符合WiMAX的一個收發機,並且在電路設計上做了許多的簡化設計,希望能對無線網路有所助益。


    With the growth of the Internet, wireless communications also becomes very popular. But the wireless local area network (WLAN) couldn’t achieve the needs of the people. Therefore, Worldwide Interoperability for Microwave Access (WiMAX) striver to spread the wideband wireless networks communication. It is also called wireless metropolitan area network (WMAN) or (WiMAX by Intel). In order to enlarge coverage, IEEE introduces IEEE std. 802.16-2004 as wireless metropolitan area network.

    In the proposed thesis, it provides one baseband processor. First, building the models of the transmitter, the wireless channel, and the receiver by using SystemC language. This thesis focuses on the proposed receiver that not only overcomes the effects of the wireless channel, but also restores the modulated data. In system simulations, it can prove that the function works correctly. Then, using Verilog language to design and implement the circuit. Finally, verifying the circuit on FPGA.

    In the architecture of the proposed receiver, it adopts more practical algorithms to build the system. That is that the performances can achieve the basic effect basic on the simplifying algorithms. For the circuit design, it uses MSB of the signals to replace the signal in order to release the complexities of the frame detector and frame synchronization. For frequency synchronization, it adopts the pipeline stages to implement the circuit. This thesis not only builds a whole transceiver conforming to WiMAX, but also designs many simplifying circuit for the proposed system. I hope it is useful for the wireless network.

    1 Introduction 1 1.1Background . . . . . . . . . . . 1 1.2Motivation . . . . . . . . . . . . 2 1.3OFDM Baseband System Model. . . . . . . 6 1.4Thesis Organization. . . . . . . . . 6 2 Physical Layer Specifications 7 2.1OFDM symbol and subcarrier definition . . 7 2.2The architecture of the transmitter . . . . 12 2.3Channel Coding . . . . . . . . . . . 12 2.3.1Randomization. . . . . . . . . . .12 2.3.2Reed-Solomon Encoder . . . . . . . . 13 2.3.3Convolutional Encoder . . . . . . . . 14 2.3.4Interleaver . . . . . . . . . . . 15 2.4Data Modulation and Pilot Modulation. . . . 17 2.4.1Data Modulation . . . . . . . . . .17 2.4.2Pilot Modulation . . . . . . . . . 19 2.5Preamble Structure and Modulation . . . . 20 2.6Frame Structure . . . . . . . . . . 23 3 Architecture Design 25 3.1Transmitter Architecture . . . . . . . . . . . . 25 3.2Receiver Architecture . . . . . . . . . 26 3.2.1Frame Detection . . . . . . . . . . 29 3.2.2Frame Synchronization . . . . . . . 30 3.2.2.1Frame Synchronization of the Short Preamble 30 3.2.2.2Frame Synchronization of the Long Preamble 31 3.2.3Frequency Synchronization . . . . . . . 32 3.2.3.1Coarse Frequency Synchronization . . . . 32 3.2.3.2Fine Frequency Synchronization . . . . . 33 3.2.4Fast Fourier Transform (FFT) . . . . . . 34 3.2.5Channel Estimation and Equalizer . . . . . 36 3.2.5.1Channel Estimation and Interpolator . . . 36 3.2.5.2Equalizer . . . . . . . . . . . 39 3.2.6Channel Tracking and Timing Synchronization. 39 3.2.6.1Channel Tracking . . . . . . . . . 40 3.2.6.2Timing Synchronization . . . . . . . 40 3.2.7Phase Compensation . . . . . . . . . 41 3.2.8QAM Slicer . . . . . . . . . . . . 42 4 Functional Simulation 45 4.1Stanford University Interim (SUI) simulation channel Model . . . . . . . . . . . . . . . 45 4.2Baseband Channel Model . . . .. . . . . 46 4.2.1Rayleigh Fading . . . . . . . . . . 47 4.2.2Carrier Frequency Offset . . . . . . . 48 4.2.3AWGN . . . . . . . . . . . . . 50 4.2.4Timing Offset . . . . . . . . . . 51 4.3Simulation Results . . . . . . . . . 51 4.3.1The Introduction of the Simulation Conditions . 52 4.3.2The Performance of the Frame Detection . . . 54 4.3.3The Performance of the Frame Synchronization. . 55 4.3.4The simulation result of the BER for AWGN . . 58 4.3.5The comparisons with/out carrier frequency offset and sampling frequency offset . . . . . . . . . 59 4.3.6The Performance of the Equalizer . . . . . 63 4.3.7The Performance of the Channel Tracking . . . 64 4.3.8The simulation result of the BER for SUI channel model . . . . . . . . . . . . . . . 64 4.4Word-Length Determination . . . . . . . . 67 5 Circuit Design 73 5.1Frame Detection . . . . . . . . . . . . . . 73 5.2Frame Synchronization . . . . . . . . . 75 5.3Frequency Synchronization . . . . . . . . . . . . 78 5.4FFT . . . . . . . . . . . . . . . . 82 5.5Channel Estimator . . . . . . . . . . 87 5.6Timing Synchronization . . . . . . . . . 88 6 Discussions and Conclusions 91 6.1Discussions . . . . . . . . . . . . . 91 6.2Conclusions . . . . . . . . . . . . . 92

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